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Hi, I was wondering if anyone could explain CAS Latency to me. I always here that the lower it is the better, as with any form of latency, but I don't understand why it gets higher with larger densities and clock speed in RAM and why DDR1 had timings of 2-3(please explain how the timings are measured if you can) but was slower than DDR2, and a similar story with DDR3.

 

 

Thank you for any responses.

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Bandwidth (1600MHz, 1866MHz, etc.) is a measure of how many cycles the RAM performs per second (mega is the prefix for million, so DDR3 1600 would be 1,600 million or 1.6 billion effective Hertz, 1.6 billion cycles per second).  CAS latency is how many cycles it takes for the RAM to get back to the CPU after the CPU makes a request to the RAM.  The amount of time does not really change between generations, just the bandwidth doubles.  So from DDR2 800, we moved to DDR3 1600, and the CAS Latency went from 4-5 to 9-10, even though the amount of time it takes for the RAM to respond to a CPU request has not changed, it is because the RAM has doubled in speed so the amount of cycles it performs in that amount of time doubles.  Instead of 5 cycles passing, 10 cycles pass in that time because the RAM is clocked twice as fast. So in essence CAS latency doesn't really get "worse" from one generation to the next despite popular belief.  It stays the same in reality as far as the latency time goes.

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Bandwidth (1600MHz, 1866MHz, etc.) is a measure of how many cycles the RAM performs per second (mega is the prefix for million, so DDR3 1600 would be 1,600 million or 1.6 billion effective Hertz, 1.6 billion cycles per second).  CAS latency is how many cycles it takes for the RAM to get back to the CPU after the CPU makes a request to the RAM.  The amount of time does not really change between generations, just the bandwidth doubles.  So from DDR2 800, we moved to DDR3 1600, and the CAS Latency went from 4-5 to 9-10, even though the amount of time it takes for the RAM to respond to a CPU request has not changed, it is because the RAM has doubled in speed so the amount of cycles it performs in that amount of time doubles.  Instead of 5 cycles passing, 10 cycles pass in that time because the RAM is clocked twice as fast. So in essence CAS latency doesn't really get "worse" from one generation to the next despite popular belief.  It stays the same in reality as far as the latency time goes.

 

I shall remember this, thank you. I've never really bothered to look into it but how you described it is perfect ;)

export PS1='\[\033[1;30m\]┌╼ \[\033[1;32m\]\u@\h\[\033[1;30m\] ╾╼ \[\033[0;34m\]\w\[\033[0;36m\]\n\[\033[1;30m\]└╼ \[\033[1;37m\]'


"All your threads are belong to /dev/null"


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