skiilaa

If you omit ECC pins and only use 1 voltage pin, you can get down to 150. 300 contacts and using zigzags to equalize traces is... manageable IMO.

That's not the point. Did you even read the link?

Instead of replacing the DIMM sockets, you could make a 2 DIMM wide PCB and socket the chip on that. That way you don't need more layers in the motherboard, you can just do the layers on your own PCB. You could still make it fit under big coolers I think. But if you're gunning for a custom motherboard, that would probably be a good choice.

You can use Display Driver Uninstaller to be safe, but it should work without it.

Both have the same memory and clock speeds AFAICT so pick whichevers cheaper/has better design

That'd be interesting. So, you'd want to attach this straight to the interposer? Or to the chipset?

Oh right, sorry, I was thinking about cycle exec rates and not pure clock frequency. I'm pretty sure that they would tolerate that, but I'm pretty sure it wouldn't be able to handle raw 100 KHz DRAM+NAND speeds. You could buffer the pages with a DRAM that runs on about the same frequency as the microcontroller I think. I don't really understand what you mean there but it sounds interesting

https://superuser.com/questions/1097402/is-esd-a-serious-risk-on-modern-machines Just because you don't experience it anymore doesn't mean that it doesn't exist.

A lot of people watching this video thought that this product would enable them to use an M.2 disk as RAM. Let's talk about that. DIMM memory modules have 2 main parts: DRAM chips, for data storage. An SPD, a standardized EEPROM chip that contains data about the memory module's size, manufacturer, and also usually includes a temp. sensor Let's look at the DRAM interface. A0-16 (A17 too on x4 chips) are address lines. DQL0-7, DQU0-7 (actually DQ0-15, but messy schematic) are the data lines. BG0 (and sometimes BG1) are bank group lines. BA0-BA1 are bank address lines. This is the interface for x16 DRAM chips. x16 means that there are 16 bits of stored data per address (DQ0-15). There are also x4 and x8 chips. DDR4 is an x64 interface, so multiple chips need to be wired up to one data bus like so: You can see that, since these chips are x16, the data lines are offset by 16 from one chip to the next. This is essentially combining 4 16-bit values into a 64-bit value. But, the addresses stay the same, since the location of the value doesn't change across the chips. The current chip we are looking at is a 16 GiB chip. This size is the biggest size officially supported by the 79-4C standard from JEDEC, so we are not going to look at some weird 64GiB chips from Micron. So, by this logic, the biggest, standard-supported DIMM stick would be 16 gigs, right? No. Enter Ranking. Ranking is a way to select between chips for more storage. DDR4 supports 4 chip select lines. These connect to one of the four ranks' chips. This way, you can essentially "filter" which of the chips receive the command that is sent on the data/address lines, so you can separate multiple x64 chip groups. So, with 4 ranks available, our maximum capacity of a DDR4 DIMM would be 4*16GiB = 64 GiB. Note, that Crucial has actually made a 128GiB DDR4 RAM stick, but it's based on LRDIMM technology, which is mostly different from normal DIMMs. Wow, this section is way longer than I expected, but, this means that our SSD-based DIMM module would only be able to have a maximum of 64 GiB of capacity, assuming that we aren't using LRDIMM. Another huge problem with this is speed. DRAM cached SSDs generally have less than 10 microseconds of access time, which sounds fast, until you look up how fast DDR4 is. Even at the lowest clock speed of 1600 MHz, the transfer time of data is 0.625 nanoseconds. To put that into perspective, that means that the slowest DDR4 DIMM out there is 16000x faster than a 10 μs SSD. And that's not even mentioning overhead. The interface of NAND chips and DRAM chips are pretty much nothing alike. You would need a microcontroller that runs at least at 1600 MHz * 2 or more (instructions don't only take 1 cycle to execute in most cases) to parse incoming commands, translate it to the NAND's interface, and repeat backwards. So, what if you build this, write microcontroller code and you have a "working" DIMM. Well, you probably can't use it. Both Intel's and AMD's memory controllers would probably shit themselves while trying to handle this (although I don't know for sure because closed-source, grrr). The problem is, you are breaking a lot of JEDEC standards by doing this, so the chances of it not working are very high. TLDR: Max capacity would be 64 GiB. It would be about 16000x slower than a DDR4 DIMM if you're using a DRAM-cached SSD, and the memory controller would probably not like it at all. You would also need to write microcontroller code to translate instructions, because of interface incompatibility.

where you put a rubber band on the handle of the tripod, and pull on it so it rotates more smoothly

Here’s the Manfrotto. This doesn’t have a handle, so I (think) I can’t use that method? Any other tricks, or should I just rotate it with my hand?

I’m not sure. I’ve attached a photo. I can also borrow a Manfrotto tripod and maybe buy one later on.

I have a Canon EOS 5D Mark ii, and I'm wondering if anyone has tips for recording B-Rolls with a tripod. It has a handle, but the "rubber band method" I've seen at a couple of places didn't work.