RAID 0 question, CPU vs Chipset RAID

[brighttail]

Okay so new question.  Right now I'm trying to see if I can work with a 28 lane CPU.  Looking at various motherboards, many PCI-e lanes and even m.2 slots are disabled on many if you are using a 28 lane CPU.

 

On a board like the new Asus Apex VI, there are two DIMM.2 slots that each hold 2 M.2 drives.   One slot is attached to the CPU while the other is attached to the Chipset.  Due to limitations of the 28 lane CPU, the DIMM.2 that is on the CPU side will have one of the m.2 slots disabled.  The DIMM on the chipset side will still allow 2 M.2s.  I know that if you create a RAID 0 drive using software and using the PCI-e lanes from the CPU, you can get the full 32Gb/s bandwidth. 

 

My question is if the DIMM.2 slot is attached to the chipset, would a RAID 0 drive get the full 32Gb/s bandwidth or would it be limited to 3.5Gb/s due to the limitations of the chipset?  I ask this because I remember the z170/z270 would allow you to create a bootable RAID 0 But the bandwidth was limited to 3.5GB/s because it was going through the chipset.  I'm wondering if this will have the same issue?

 

Thanks.

[Technomancer__]

If its a x299 system you are going to buy better get threadripper

Its cheaper and all CPUs (threadripper) have 64 pcie lanes

[brighttail]

Just now, Ethocreeper said:

If its a x299 system you are going to buy better get threadripper

Its cheaper and all CPUs (threadripper) have 64 pcie lanes

Thank you for that tidbit and believe me I've been looking, but that doesn't answer the question I have poised here.

[Technomancer__]

Dmi 3.0

Quote

It is used to link an Intel CPU with the Intel Platform Controller Hub (PCH), which supersedes the historic implementation of a separate northbridge and southbridge. DMI 3.0, released in August 2015, allows the 8 GT/s transfer rate per lane, for a total of four lanes and 3.93 GB/s for the CPU–PCH link.

https://goo.gl/images/kC1Q1M

 

 

[Technomancer__]

Just now, Ethocreeper said:

Dmi 3.0

https://goo.gl/images/kC1Q1M

 

 

Note: the cpu - chipset banwith is shared with everything on the the chipset

[brighttail]

1 minute ago, Ethocreeper said:

Note: the cpu - chipset banwith is shared with everything on the the chipset

I'm still confused then. I think it has to do with the Apex board itself as it says that those Two DIMM.2 slots, one is expressly for the CPU PCI-e lanes and one is for the Chipset lanes.  I was told if we try to make a bootable RAID 0 with non-intel drives, we have to use the Chipset which means it would have to go through the DMI.  As you have shown it tops out at 3.5GB/s.  Modern M.2s would saturate this almost completely with one m.2.

 

I was hoping that if you didn't try a bootable, that the DIMM.2 would try to use the PCI-e lanes instead of the DMI.  It doesn't seem like that is an option.  Almost makes you wonder WHY Asus even put in a DIMM.2 that only goes through the chipset..  Course I could still be all wrong about this.  I really need to see the schematics of the APEX board.  I know the Rampage extreme 6 has a DIMM.2 slot that a user can choose in the BIOS which lanes it gets to use.

[brighttail]

"X299 will support RAID with up to three PCIe 3.0 x4 devices. However in order to get the maximum peak bandwidth, motherboard manufacturers will have to derive all the ports from the CPU, not the chipset.. "

 

And this answers my question.  On this particular board one of the DIMM.2 slots is right to the chipset.  It is almost as if Asus is working with Intel to force people to buy a 10 core  CPU with 44 lanes.

[Technomancer__]

17 minutes ago, brighttail said:

  It is almost as if Asus is working with Intel to force people to buy a 10 core  CPU with 44 lanes.

Or threadripper