division in VHDL

[digitalMaster]

hello guys ,

Do you have any code for division in vhdl?

If its possible without for

Thank you in advance

[nlhans]

Are you implementing this for a device already, or purely for synthesis?

What data types are you working with?

Is it a divide by 2, 4, 8 by coincidence? In that case a bit shift is more economical.

Otherwise I would consider converting std_logic_vector to numeric; doing the division and then converting back to a std_logic_vector.

The VHDL compiler may choose how to implement it wants, however it may become very resource consuming because in this case it requires 1-cycle division.