Just to add this in, as it wasn't included in the video.
AMD's ECC for Ryzen is not POR (plan of record), which means it isn't post validated. A system can very well say it's running ECC, and it'll show in the options that ECC is running, but that doesn't actually tell you if ECC is enabled. The only way to truly see if it's enabled is to force a bit-flip and see if it catches it.
I responded to Torvalds' thread on RWT with this info at the time.
Secondary, DDR5 has ECC per chip, not per module. It's quite a different and important distinction designed mostly for the memory cell reliability than correcting errors. Most DDR5 for consumers will be non-ECC, and ECC variants of DDR5 still require that 9th chip to enable true SECDED support.
FlowOnShow reacted to IanCutress in Linus was right.
