We're now squishing even more on a 14nm die! (Just another day at Intel) Comet Lake!

[CarlBar]

Microarchitecture is entirely defined by how you want the CPU to function internally. And the physical locations of the components, so long as they're not excessively separated, doesn't change that at all.

[Nicnac]

58 minutes ago, mynameisjuan said:

Intel vs AMD

Windows vd MacOS

Android vs IOS

Nvidia vs AMD

 

Instant flame war any time anyone mentions the competitor. 

There fixed it for ya 

[kting15]

Hello Skylake my old friend... I've come to update you again...

[Brooksie359]

3 hours ago, CarlBar said:

Microarchitecture is entirely defined by how you want the CPU to function internally. And the physical locations of the components, so long as they're not excessively separated, doesn't change that at all.

I don't think you understand how a good chiplet design works. Zen is good because it was designed to be scalable while the ring bus is not. The ring bus is designed around really fast access to memory and resources but when you change where those resources are and how you need to access them then it requires a new microarchitecture design. If that wasn't the case then Intel would have been using ring bus for their large server chips a long time ago. If you want to speculate about what ifs the go ahead but that doesn't mean Jack right now. Intel is struggling and will continue to struggle until they figure things out with 10nm. 

[mynameisjuan]

2 hours ago, Nicnac said:

There fixed it for ya 

Oh you gone done did it now

[CarlBar]

3 hours ago, Brooksie359 said:

I don't think you understand how a good chiplet design works. Zen is good because it was designed to be scalable while the ring bus is not. The ring bus is designed around really fast access to memory and resources but when you change where those resources are and how you need to access them then it requires a new microarchitecture design. If that wasn't the case then Intel would have been using ring bus for their large server chips a long time ago. If you want to speculate about what ifs the go ahead but that doesn't mean Jack right now. Intel is struggling and will continue to struggle until they figure things out with 10nm. 

 

Yeah but once again if intel had been pursuing a chiplet design before now they would only now be getting towards the point where a ring bus becomes unwieldy.

 

I think the core disconnect here is your going "what would intel need to do to implement Epyc", while i'm going "What would intel need to implement the 9900k as a chiplet design".

 

Doing the 9900k as a chiplet design wouldn't need any real significant changes bcause you could continue to use an interposer based ring bus for the whole thing. And i very much doubt the 9900K is the limit for what could be done on a ring bus, i'll admit i'm not sure exactly where the limit for a ring bus setup is but it's certainly above the 9900K, and good as Zen 2 is going to be, unless AMD are willing to wind up their thermals as well, (which the AM4 socket only has limited space to do), there's a practical limit to how far they could push it, (the limit is still a scary place mind but it's not beyond intels ability to match it).

 

 

Where's an intel chiplet design started waaaay back would be on a physically larger socket to accommodate the multiple dies and the thus have the better spread out thermals and greater cooler contact area to give intel the ability to manage the thermals despite their inferiour process power efficiency.

[williamcll]

Imagine if tangle lake quantum processor is 14nm as well.

 

The sky(lake)'s the limit!

[leadeater]

3 hours ago, CarlBar said:

Yeah but once again if intel had been pursuing a chiplet design before now they would only now be getting towards the point where a ring bus becomes unwieldy.

It's been very unwieldy already on the Xeon side, that's why Skylake-SP moved to Mesh. The HCC dies had dual ring bus to help compensate but that in itself had problems depending on workload, only the really highly specialized stuff. A lot of the HPC clusters stuck with the highest clock rate highest core count MCC die with only a single ring bus to avoid problems with core, cache and I/O latency and sync problems. You can lose a great deal of efficiency if you're not careful and net no actual performance increase even when the sum of all parts is supposed to be a more powerful configuration. That's really not applicable to the general person or business though, that's an entire field of IT of it's own that I only have general interactions with as I'm in the corporate side of IT where I work not the research side.

 

3 hours ago, CarlBar said:

And i very much doubt the 9900K is the limit for what could be done on a ring bus

 Topped out at either 14 or 16 cores on the Xeon product line, I forget exactly which but it's easy enough information to find out.

[Brooksie359]

8 hours ago, CarlBar said:

 

Yeah but once again if intel had been pursuing a chiplet design before now they would only now be getting towards the point where a ring bus becomes unwieldy.

 

I think the core disconnect here is your going "what would intel need to do to implement Epyc", while i'm going "What would intel need to implement the 9900k as a chiplet design".

 

Doing the 9900k as a chiplet design wouldn't need any real significant changes bcause you could continue to use an interposer based ring bus for the whole thing. And i very much doubt the 9900K is the limit for what could be done on a ring bus, i'll admit i'm not sure exactly where the limit for a ring bus setup is but it's certainly above the 9900K, and good as Zen 2 is going to be, unless AMD are willing to wind up their thermals as well, (which the AM4 socket only has limited space to do), there's a practical limit to how far they could push it, (the limit is still a scary place mind but it's not beyond intels ability to match it).

 

 

Where's an intel chiplet design started waaaay back would be on a physically larger socket to accommodate the multiple dies and the thus have the better spread out thermals and greater cooler contact area to give intel the ability to manage the thermals despite their inferiour process power efficiency.

And if Intel had never commited anti competitive practices when AMD had the better processors and allowed AMD to get more money for R&D then they would have a superior design capable of beating the ring bus architecture outright. You see how useful speculation is? Again the ring bus architecture was never designed for chiplet and it isn't as simple as connecting a bunch together with some sort of interface like infinity fabric. 

[pas008]

i'm hoping amds node shrink shows something useful for us

 

32nm to 14++++++

has showed us really nothing

seriously what has it showed us on cpus? maybe 400mhz on frequency for intel?

[DrDerp]

1 minute ago, pas008 said:

i'm hoping amds node shrink shows something useful for us

 

32nm to 14++++++

has showed us really nothing

seriously what has it showed us on cpus? maybe 400mhz on frequency?

It has had a decent increase in IPC and especially has helped Power Consumption. What I am personally looking forward to is having AMD finally get long battery life in a laptop rather than trying for unlimited power! because IMO, how powerful the CPUs are right now is honestly fine, if they can just decrease power consumption and increase battery life to great times, I would definitely buy one of their laptops.

[porina]

6 hours ago, leadeater said:

Topped out at either 14 or 16 cores on the Xeon product line, I forget exactly which but it's easy enough information to find out.

In a quick search, this article suggests Broadwell went up to 12 cores per ring.

https://www.anandtech.com/show/11550/the-intel-skylakex-review-core-i9-7900x-i7-7820x-and-i7-7800x-tested/5

 

Dunno about Haswell or earlier.

 

Edit: Haswell-EP apparently up to 10 cores on a ring:

https://www.anandtech.com/show/8423/intel-xeon-e5-version-3-up-to-18-haswell-ep-cores-/4

 

[pas008]

24 minutes ago, DrDerp said:

It has had a decent increase in IPC and especially has helped Power Consumption. What I am personally looking forward to is having AMD finally get long battery life in a laptop rather than trying for unlimited power! because IMO, how powerful the CPUs are right now is honestly fine, if they can just decrease power consumption and increase battery life to great times, I would definitely buy one of their laptops.

isnt a node shrink completely independant of ipc (arent they technically getting more transistors in smaller area)

hence why node shrinks hardly gave any benefit except raising the power to match last gen?

isnt ipc the improvements on the isa?

 

someone bring more light to this

[leadeater]

34 minutes ago, porina said:

In a quick search, this article suggests Broadwell went up to 12 cores per ring.

https://www.anandtech.com/show/11550/the-intel-skylakex-review-core-i9-7900x-i7-7820x-and-i7-7800x-tested/5

 

Dunno about Haswell or earlier.

 

Edit: Haswell-EP apparently up to 10 cores on a ring:

https://www.anandtech.com/show/8423/intel-xeon-e5-version-3-up-to-18-haswell-ep-cores-/4

 

Ah yes that's correct, 12-14 was MCC. Edit: Skylake-SP LCC is also 10 cores interestingly enough, even with the Mesh change.

 

On that note I find it odd that Intel would need or want to implement dual ring on a 10c desktop CPU when it wasn't required for Xeons.

[leadeater]

38 minutes ago, pas008 said:

isnt a node shrink completely independant of ipc (arent they technically getting more transistors in smaller area)

hence why node shrinks hardly gave any benefit except raising the power to match last gen?

isnt ipc the improvements on the isa?

 

someone bring more light to this

Yes that is correct, a node shrink allows you to make changes that could increase the IPC as you have more transistors in the same die area but it's the architecture itself that sets the IPC. Nodes are purely the physical aspect which does influence the architecture design, but not to the level where you could say a node shrink increases IPC.

[porina]

17 minutes ago, leadeater said:

On that note I find it odd that Intel would need or want to implement dual ring on a 10c desktop CPU when it wasn't required for Xeons.

Maybe it is a misunderstanding somewhere. You could argue each ring set is actually two rings, running in opposite directions. Like the common confusion between real clock and rated transfer rate of DDR ram.

[CarlBar]

7 hours ago, leadeater said:

It's been very unwieldy already on the Xeon side, that's why Skylake-SP moved to Mesh. The HCC dies had dual ring bus to help compensate but that in itself had problems depending on workload, only the really highly specialized stuff. A lot of the HPC clusters stuck with the highest clock rate highest core count MCC die with only a single ring bus to avoid problems with core, cache and I/O latency and sync problems. You can lose a great deal of efficiency if you're not careful and net no actual performance increase even when the sum of all parts is supposed to be a more powerful configuration. That's really not applicable to the general person or business though, that's an entire field of IT of it's own that I only have general interactions with as I'm in the corporate side of IT where I work not the research side.

 

 Topped out at either 14 or 16 cores on the Xeon product line, I forget exactly which but it's easy enough information to find out.

 

I'm aware you can look it up, i've even read something on it but at the time i couldn't remember the exact value ;). I just knew it was greater than 8.

 

As for why they're using a double ring bus on comet lake. Again i think they're going to put 2 8700K dies with microarchitecture improvements on the same cpu.

 

In fact i'm going to make an extra prediction. One of the dies will have the IGPU replaced by a big piece o L4 cache. But in case going with 2 8700K dies with the worst core disabled should let intel push the frequencies harder. We know from retailer binning that the 14nm+ process could produce 8700K's capable of a 5.3Ghz all core OC so with the worse core out of the loop and the use of a 14nm+++ process i wouldn't be surprised to see that achieved as the boost frequency in a normal chip.

 

2 hours ago, Brooksie359 said:

And if Intel had never commited anti competitive practices when AMD had the better processors and allowed AMD to get more money for R&D then they would have a superior design capable of beating the ring bus architecture outright. You see how useful speculation is? Again the ring bus architecture was never designed for chiplet and it isn't as simple as connecting a bunch together with some sort of interface like infinity fabric. 

 

Actually because of how the ring bus works, (at least what i've seen of it in explanations), you can just use it as is to connect everything on a chiplet as thats what it allready does on the monolith setup, your just changing the locations of the physical components on the cpu substrate.

[Brooksie359]

37 minutes ago, CarlBar said:

 

I'm aware you can look it up, i've even read something on it but at the time i couldn't remember the exact value ;). I just knew it was greater than 8.

 

As for why they're using a double ring bus on comet lake. Again i think they're going to put 2 8700K dies with microarchitecture improvements on the same cpu.

 

In fact i'm going to make an extra prediction. One of the dies will have the IGPU replaced by a big piece o L4 cache. But in case going with 2 8700K dies with the worst core disabled should let intel push the frequencies harder. We know from retailer binning that the 14nm+ process could produce 8700K's capable of a 5.3Ghz all core OC so with the worse core out of the loop and the use of a 14nm+++ process i wouldn't be surprised to see that achieved as the boost frequency in a normal chip.

 

 

Actually because of how the ring bus works, (at least what i've seen of it in explanations), you can just use it as is to connect everything on a chiplet as thats what it allready does on the monolith setup, your just changing the locations of the physical components on the cpu substrate.

It wasn't meant to scale with multiple chiplets. The entire point of the architecture was to eliminate the need for each core to be wired to the cache. As soon as you start trying to strap a bunch of rings to the same cache you essentially return to the problem they had with the designs prior to the ring bus architecture. Essentially you won't really reap the benefits of the architecture if you try to scale up the ring bus architecture. You might be able to tie 2 together but scaling beyond that doesn't make sense and would require a new architecture. Zen was designed to be highly scalable while the ring bus was not. Again you are talking about pure hypotheticals to begin with so you might as well just admit that Intel doesn't currently have an answer to what AMD has coming out. 

[CarlBar]

1 hour ago, Brooksie359 said:

It wasn't meant to scale with multiple chiplets. The entire point of the architecture was to eliminate the need for each core to be wired to the cache. As soon as you start trying to strap a bunch of rings to the same cache you essentially return to the problem they had with the designs prior to the ring bus architecture. Essentially you won't really reap the benefits of the architecture if you try to scale up the ring bus architecture. You might be able to tie 2 together but scaling beyond that doesn't make sense and would require a new architecture. Zen was designed to be highly scalable while the ring bus was not. Again you are talking about pure hypotheticals to begin with so you might as well just admit that Intel doesn't currently have an answer to what AMD has coming out. 

 

In case you managed to miss it i literally a couple of days ago upgraded to an X470 2700X CPU/MB setup. I'm very aware of AMD vs Intel's current position. The point is was trying to make originally that seems to have gone straight over your head is that the limit isn't the performance per core per clock cycle of intel's current process or architecture design. Even with everything we have on Zen2 says AMD is at best going to get parity there.. Intels sole issue is their ability to handle both high core counts and high clock speeds on the same CPU due to thermals. And their lack of a chiplet design is a far bigger limiter there than their lack of a new process node.

 

Somehow that seems to have gotten lost in our microarchitecture argument.

 

As far as the upcoming chip. I doubt, (now i've had time to consider it more), that they're going to have each chiplet connected to each other via overlapping ring busse,s they'll probably work through the L4 cache which they can re-use the undeeded IGPU links on the die with the IGPU swapped out to handle. That or their going t build their multi-socket xeon tuff directly onto their desktop chips but i don't buy that. Too many potential software issues.

[Tellos]

I dont think a core count raise is coming from zen2 I think a clock speed and IPC gain is coming which is what they really need.