We're now squishing even more on a 14nm die! (Just another day at Intel) Comet Lake!

[The Benjamins]

4 hours ago, imreloadin said:

The 4770K was a Haswell chip, I believe Kaby Lake was the 7700K.

My bad, my brain didn't work. I meant haswell.

[GoldenLag]

Just now, VegetableStu said:

oh right, what about APUs? would they do a separate Vega/Navi die to replace one die for 4xxxG? o_o

ive got no idea. its possible, while it is also probably the only way to get it to work. dont know how it will play out with the substrate, or if it would need to be a different substrate. 

[Coaxialgamer]

While (10nm==!ready)

    refresh all the things

[CarlBar]

1 hour ago, VegetableStu said:

hmm...

• 1 CCX = 4C, 1 die = 2CCX = 8C
• TOTL EPYC Rome = 64C
• TR Gen 3:
  • "3990WX" = 64C?
  • 2970WX had 3/4 active cores than 2990WX
    "3970WX" = 48C?
  • would AMD just half the number of dies or active cores like TR Gen 1?
• Ryzen Gen 3:
  • 4 die R7?
    "R7 3700X" = 32C?! okay that's too much
  • 4 dice with half the active cores, or 2 dice with all active? (which gets higher frequencies?)
    "R7 3700X" = 16C? Intel's Comet lake desktop rumored to top out at 10C, so this is more likely
  • R5 x6xx had 3/4 than R7 as well
    "R5 3600X" = 12C?
  • "R5 3500X" = 8C? would AMD even need to turn on multithreading here? (considering the 9700K is already a 8C8t part)

/end daydream

 

The real catch with all of that is that AMD has hinted but not quite come out and confirmed that each 8 core chiplet is one ccx.

[porina]

38 minutes ago, VegetableStu said:

 

As long as it is F5 and not F for Intel...

[GoldenLag]

4 minutes ago, VegetableStu said:

wait, so each die has 1 CCX has 8 cores now? o_o

Nothing confirmed. Only speculation afaik.

 

Its possible and somewhat likely

[Brooksie359]

4 hours ago, CarlBar said:

 

Don't confuse a well optimized design for an inherently superior one. The absolute minimum latency is (naturally), directly related to the propagation of the signal through the conductive medium and the length of the path it must traverse. However the real world values are allways constrained more by other factors than this one. That's important overall as it means that changing from the current design to a chiplet design isn't going to cause major latency changes due to the changes in physical positioning of components. It's all going to come down to the underlying design of the other components of the interconnects really. And it's obvious intel knows exactly what they're doing when it comes to that. To be fair i suspect AMD does too, but it's also obvious that he Zen1 and Zen+ Memory controllers and IF fabric links weren't really anywhere near as robust as would have been ideal.

 

Don't get me wrong i'm not saying there would be no impact on intel interconnect latency, but i think your severely overestimating how extreme it would be.

 

Personally long term if HBM3 lives up to it's name i'm expecting chip manufacturers to start integrating that onto dies, (or possibly building their CPU's a bit differently so that the HBM is on an interposer that the CPU then sits in letting you mix and match HBM3 dies with CPU's but thats severe speculation), with high endurance non-volatile memory, (like 3Dx-point and Z-NAND), taking up DIMM slots. That would offer even lower latency volatile memory to CPU's and a much faster high capacity non-volatile storage for whatever programs stuff is currently being used.

Again that is pure speculation. You can talk about how they obviously know what they are doing so they would implement it well but that is speculation. The simple truth is nobody knows how good of an implementation they would create. This is a pure hypothetical situation and isn't where we find ourselves today so it really doesn't matter anyways.  

[Brooksie359]

1 minute ago, GoldenLag said:

Nothing confirmed. Only speculation afaik.

 

Its possible and somewhat likely

Didn't they confirm that each chiplet had 8 cores when they showed off the 64 core server cpu? I am unsure what that would mean for ccx though. 

[LeSheen]

16 hours ago, mate_mate91 said:

Probably higher temperatures too...

actually its the opposite. Smaller proces is less current needed so less excess heat produced.

And more overclocking headroom as a result.

[GoldenLag]

15 minutes ago, Brooksie359 said:

Didn't they confirm that each chiplet had 8 cores when they showed off the 64 core server cpu? I am unsure what that would mean for ccx though. 

No, they told us the CPU had 64 cores. 8 cores in each chiplet. No word on CCX layout or if there even is one.

[The Benjamins]

2 hours ago, VegetableStu said:

hmm...

• 1 CCX = 4C, 1 die = 2CCX = 8C
• TOTL EPYC Rome = 64C
• TR Gen 3:
  • "3990WX" = 64C?
  • 2970WX had 3/4 active cores than 2990WX
    "3970WX" = 48C?
  • would AMD just half the number of dies or active cores like TR Gen 1?
• Ryzen Gen 3:
  • 4 die R7?
    "R7 3700X" = 32C?! okay that's too much
  • 4 dice with half the active cores, or 2 dice with all active? (which gets higher frequencies?)
    "R7 3700X" = 16C? Intel's Comet lake desktop rumored to top out at 10C, so this is more likely
  • R5 x6xx had 3/4 than R7 as well
    "R5 3600X" = 12C?
  • "R5 3500X" = 8C? would AMD even need to turn on multithreading here? (considering the 9700K is already a 8C8t part)

/end daydream

I see it being due to a lack of competition, they can just release higher core count on 7nm+ or mid generation if needed.

Server: 64c128t 

HEDT: 48c96t (no need to release a 64c this gen)

Mainstream: 12c24t (no need to release 16c this gen)

[GoldenLag]

5 minutes ago, The Benjamins said:

I see it being due to a lack of competition, they can just release higher core count on 7nm+ or mid generation if needed.

Server: 64c128t 

HEDT: 48c96t (no need to release a 64c this gen)

Mainstream: 12c24t (no need to release 16c this gen)

All in the name of maximizing yields. 

 

They could literally go with two single core dies on an athlon 300GE........

 

Gonna be interesting if AMD starts holding back while intel is showing all theyve got. 

[ScratchCat]

20 hours ago, Alexzz_ said:

Raja is secretly stealing the development money for cpu's and throwing it into gpu's XD

Raja just taught them the art of refreshing a product over and over.

20 hours ago, suicidalfranco said:

tic toc toc toc toc toc toc toc toc toc toc toc toc toc toc toc toc toc toc ...

They haven't noticeably changed the architecture in a number of generations now, only pushing frequencies, adding cores and fixing hardware vulnerabilities.

[GuardEzio]

It may just be me, but it's looking ever more like Intel are panicking. AMD has got the drop on them and now they are hastily throwing what they can, where they can, in an attempt to hold their hill...

 

Must admit, I'm curious to see where Intel will be in a couple of years at this rate. 

[aliasdred]

22 hours ago, PopsicleHustler said:

I swear, there is an AMD employee working undercover at Intel with a mission to destroy Intel.

I thought Raja was working in the GPU division

[CTR640]

Lakes, lakes everywher. Maybe Intel failed at Cannon Lake, or Tiger Lake or Whiskey Lakes, what the fuck ever, Intel keeps drowning in Lakes!

[pas008]

2 minutes ago, CTR640 said:

Lakes, lakes everywher. Maybe Intel failed at Cannon Lake, or Tiger Lake or Whiskey Lakes, what the fuck ever, Intel keeps drowning in Lakes!

drowning in cash lakes

[CTR640]

1 minute ago, pas008 said:

drowning in cash lakes

That's exactly what I wanted to say lol

[LukaH]

 

Intel right now.

[ravenshrike]

1 minute ago, LukaH said:

 

Intel right now.

Intel wishes they had something as smart as manatees. Instead they've got koala bears.

[NumLock21]

23 hours ago, PopsicleHustler said:

I swear, there is an AMD employee working undercover at Intel with a mission to destroy Intel.

 

Former AMD employees that went to Intel

 

 

 

From WCCF

Me

[PopsicleHustler]

23 minutes ago, NumLock21 said:

 

Former AMD employees that went to Intel

 

 

 

From WCCF

Me

Haha, now it all makes sense!

[flibberdipper]

Nothing like Broadwell+++++

[CarlBar]

2 hours ago, Brooksie359 said:

Again that is pure speculation. You can talk about how they obviously know what they are doing so they would implement it well but that is speculation. The simple truth is nobody knows how good of an implementation they would create. This is a pure hypothetical situation and isn't where we find ourselves today so it really doesn't matter anyways.  

 

Um no it's not pure speculation. Unlike you i apparently have an idea about the laws of physics. Based on that we flat out know that neither intel nor AMD are at the limit of the theoretical on their latency.

 

That leave the two design factors to get in the way. Bandwidth and routing hardware latency. The thing is both of those are entirely dependent on the quality of the design of various component in the links. The thing is that hardware is not magically going to get way worse because you move it to a chiplet design. So we know intel is capable of producing a low latency chiplet design. They have to screw up by the numbers to not do so.

 

Now Comet Lake i think will have some issues if it's a 2 die design, but thats because they're functionally taking existing tech and littrially gluing it together, it's going to be a massive bodge job, with obvious consequences compared to a designed from the ground up solution. Though in theory if they do it right they should still only have bad latency between a few of the cores.

[NumLock21]

14 minutes ago, PopsicleHustler said:

Haha, now it all makes sense!

Another one joins Intel

 

https://www.fudzilla.com/news/47506-ex-amd-chaps-snatch-another-executive-for-intel