Intel announces Cascade Lake AP

[porina]

Quote

Ahead of the annual Supercomputing 2018 conference next week, Intel is today announcing part of its upcoming Cascade Lake strategy. Following on from its server-focused Xeon Scalable Skylake family, Intel has already pre-announced that Cascade Lake-SP will form the next generation, with a focus on compute and security. Today’s announcement is for a product family to run alongside Cascade Lake-SP, called Cascade Lake-AP, or Cascade-AP for short. Cascade-AP is going to be aimed at ‘advanced performance’. In order to implement this new processor family, Intel is combining multiple chips in the same package.

Source: https://www.anandtech.com/show/13535/intel-goes-for-48cores-cascade-ap

 

After poking AMD for "gluing" dies together, Intel has also jumped on the train and will offer up to 48 cores per socket by using two interconnected dies. Details are not in depth yet, but the two dies will be connected via UPI, not EMIB. Per socket you get 12 ram channels, unknown PCIe connectivity and TDP, and supports two socket configurations.

 

This strategy might help Intel to keep their costs relatively in check while offering higher core counts per socket to counter AMD's EPYC offerings. As we get more details it might offer a clue as to what may come with near future desktop parts.

 

Edit: Intel links thanks to @Dylanc1500

https://newsroom.intel.com/wp-content/uploads/sites/11/2018/11/cascade-lake-advanced-performance-press-deck.pdf

https://newsroom.intel.com/wp-content/uploads/sites/11/2018/11/intel-xeon-e-2100-processor-press-deck.pdf

 

[Nowak]

1 minute ago, porina said:

After poking AMD for "gluing" dies together, Intel has also jumped on the train and will offer up to 48 cores per socket by using two interconnected dies.

Not the first time they've used multiple dies to offer multiple cores. Remember the Pentium D?

 

 

But really, that makes Intel poking at AMD for "gluing together" dies even funnier  

[19_blackie_73]

are we back to the early days of powerpoint design? looks 80s

[WereCat]

If this is going to be on 14nm+++ then I guess good luck to Intel. 

If it's going to be on 7nm then thats a long way off. 

[leadeater]

9 minutes ago, porina said:

After poking AMD for "gluing" dies together, Intel has also jumped on the train and will offer up to 48 cores per socket by using two interconnected dies.

Yea but Intel's glue is a much better special glue, it's Blue so better.

 

10 minutes ago, porina said:

Per socket you get 12 ram channels

Holy crap that's a bit over kill on the ram channels, but I guess that's the side effect of gluing 2 dies together that have 6 channels each.

 

11 minutes ago, porina said:

Details are not in depth yet, but the two dies will be connected via UPI, not EMIB.

It'll probably be UPI over EMIB, the dies themselves have to use UPI to talk across to other dies/packages as that's the dedicated interface for it and Intel hasn't done a complete re-architecture to change that.

[ravenshrike]

Im betting $23,999 per processor and single socket motherboards costing $12,000.

[WereCat]

@leadeater

There has been rumors of an Intel dual die CPU based on their current 14nm Xeon lineup with up to 350W TDP few months back, so if this is it, I really have to wonder what the clocks on this thing will be like. Below 2GHz very likely. Price will definitely be sky high and Rome is on the way with supposedly 64cores and same clocks and TDP as the current EPYC. 

This will be interesting. 

[leadeater]

5 minutes ago, WereCat said:

There has been rumors of an Intel dual die CPU based on their current 14nm Xeon lineup with up to 350W TDP few months back, so if this is it, I really have to wonder what the clocks on this thing will be like. Below 2GHz very likely.

My guess based on how Intel does their TDP and clocks etc there will be a standard TDP product set around 250W-280W TDP and a higher power/higher base clock 300W-350W TDP product set. 1.9Ghz-2.1Ghz on the lower TDP products and 2.2Ghz-2.5Ghz on the higher TDP products, boosts no idea. Cooling is going to be interesting because that is really what is going to limit the boost clocks and 2U isn't great for that.

 

Might be used in water cooled servers only, that is getting more popular after all.

[porina]

34 minutes ago, Nowak said:

Not the first time they've used multiple dies to offer multiple cores. Remember the Pentium D?

Yeah, but what have they done recently? :)

24 minutes ago, leadeater said:

Holy crap that's a bit over kill on the ram channels, but I guess that's the side effect of gluing 2 dies together that have 6 channels each.

Depends on what you do with it, but I think it is needed for more demanding uses. Even at this number, you're feeding 4 cores per channel. Assuming core clocks are not going to be too high, I'd rate this as adequate. If you really don't need them all and want to save a bit of cash, you could simply not populate them all.

24 minutes ago, leadeater said:

It'll probably be UPI over EMIB, the dies themselves have to use UPI to talk across to other dies/packages as that's the dedicated interface for it and Intel hasn't done a complete re-architecture to change that.

Was going by the source article. Seems like we're getting drip fed the information and more details will come out over time.

[Dylanc1500]

12 minutes ago, leadeater said:

My guess based on how Intel does their TDP and clocks etc there will be a standard TDP product set around 250W-280W TDP and a higher power/higher base clock 300W-350W TDP product set. 1.9Ghz-2.1Ghz on the lower TDP products and 2.2Ghz-2.5Ghz on the higher TDP products, boosts no idea. Cooling is going to be interesting because that is really what is going to limit the boost clocks and 2U isn't great for that.

 

Might be used in water cooled servers only, that is getting more popular after all.

This might be the beginning of submersion cooling trying to take off again. Who'd of thunk that Cray would have been so ahead of time.

[leadeater]

3 minutes ago, porina said:

Was going by the source article. Seems like we're getting drip fed the information and more details will come out over time.

tbh I hadn't actually read the source yet, does sound like no EMIB at all.

[leadeater]

Just now, Dylanc1500 said:

This might be the beginning of submersion cooling trying to take off again. Who'd of thunk that Cray would have been so ahead of time.

From what I've seen direct chip water cooling actually does a better job.

[porina]

1 minute ago, leadeater said:

tbh I hadn't actually read the source yet, does sound like no EMIB at all.

Line below from article.

Quote

Intel did confirm that these dies are connected by UPI over the package, and not with Intel’s EMIB technology.

You raise an interesting point, they must be using some kind of physical connection regardless of the logical connection. If not EMIB, is there a more traditional method?

[leadeater]

3 minutes ago, porina said:

You raise an interesting point, they must be using some kind of physical connection regardless of the logical connection. If not EMIB, is there a more traditional method?

And will the OS see it as 2 CPUs or 1?

 

NUMA NUMA time 

 

[toor]

1 minute ago, leadeater said:

From what I've seen direct chip water cooling actually does a better job.

 

Didn't the poach the guy from AMD?  (Jim Keller).   Can't imagine he'd be able to forget everything about them.

[Dylanc1500]

11 minutes ago, leadeater said:

From what I've seen direct chip water cooling actually does a better job.

Really? I would have thought 2 stage submersion cooling would have been better. Well I guess we learn something new every day.

 

 

Also @porina here is the actual slides from the announcements. It has a bit more information in it.

 

https://newsroom.intel.com/wp-content/uploads/sites/11/2018/11/cascade-lake-advanced-performance-press-deck.pdf

 

https://newsroom.intel.com/wp-content/uploads/sites/11/2018/11/intel-xeon-e-2100-processor-press-deck.pdf

 

I don't know if it's helpful or not, but either way.

[GoldenLag]

43 minutes ago, leadeater said:

Holy crap that's a bit over kill on the ram channels, but I guess that's the side effect of gluing 2 dies together that have 6 channels each.

How many channels will Zen 2 have then with 8 prpbable core dies (+_+)

[porina]

3 minutes ago, leadeater said:

And will the OS see it as 2 CPUs or 1?

I'd hope and assume it would be similar to Threadripper/Epyc to give the OS/apps some chance of figuring out how to optimise workloads.

 

3 minutes ago, leadeater said:

NUMA NUMA time 

I got that song in my head now. Thanks.

[leadeater]

2 minutes ago, Dylanc1500 said:

Really? I would have thought 2 stage submersion cooling would have been better. Well I guess we learn something new every day.

I think submersion is better for overall cooling but for pushing a CPU, or other die, to extreme power the direct to chip water does it better. You might be right about 2 phase immersion though, forgot that was a thing.

[0x00000001]

Linpack : up to 3.4X vs single EPYC 7601

StreamTriad : up to 1.3x vs single EPYC 7601

..... up to ... vs single EPYC 7601

Price : up to 9999x vs single EPYC 7601

[schwellmo92]

Interesting that they chose to connect two 24 core parts, why not connect their 28 core parts?

Is this also a case of Intel trying to steal AMD's thunder once again? Or did they unintentionally release it the day before AMD's event?

[GoldenLag]

4 minutes ago, schwellmo92 said:

Interesting that they chose to connect two 24 core parts, why not connect their 28 core parts?

Power and Cost perhaps?

 

Also a possibility they stepped a bit back on Diesize to be able to yield more

[leadeater]

9 minutes ago, schwellmo92 said:

Interesting that they chose to connect two 24 core parts, why not connect their 28 core parts?

Is this also a case of Intel trying to steal AMD's thunder once again? Or did they unintentionally release it the day before AMD's event?

It is the 28 core die but only utilizing 24 cores.

[asus killer]

if you can't bet them, join them. 

[mr moose]

1 hour ago, VegetableStu said:

SMURF GLUE?! O_O

 

EDIT: also someone's miffed

maybe the point was Intel wan't being obtuse when they said EPYC/TR had cores "glued together" o_o

Like everything else about Intel, facts don't seem to mean anything. Remember they Lie about TDP, Node size, performance, price, the colour of your undies and how many coolers it takes to improve a xeon. 

 

Intel market their products with all the vigor and edginess they can muster, just like AMD and Nvidia and MS and Apple and.. and... and...  and... and... and...