Ryzen's Infinity Fabric Clock Speed is Linked to Memory Clock Speed... Might Explain Why Memory OCs Make a Noticeable Impact in Performance on Ryzen?

[AnonymousGuy]

6 hours ago, DocSwag said:

Nope, it's confirmed. Straight from the Anandtech article about Ryzen 5:

 

Oh good so they're going back to the Pentium D days where it was dual cores glued together, which was ironic because AMD was the first to make a "true" quad core.

 

Naples is going to be fucked with the number of interconnects it's going to have going on.

[Doobeedoo]

Saw the G.Skill Ryzen certified memory and fastest is 3466MHz 2x8GB they list. Would like to see that running. Planning build on summer so I'd probably go with that.

Also I do wonder about BIOS updates for memory issues, how much will it differ. I'm sure current issues will be resolved so out of box it works fine, but what will be the maximum frequency it will be able to run in the end. Probably the above one, but we'll see.
Also, since desktop quad core si 2+2 between 2 CCXs potentially APUs that are quad core will be single CCX then. 

[Guest Kloaked]

All of a sudden, tons of LTT members rush to Google to type in "CPU Infinity Fabric" so that they can argue about things that they read about on Wikipedia.

[RadiatingLight]

26 minutes ago, AnonymousGuy said:

Oh good so they're going back to the Pentium D days where it was dual cores glued together, which was ironic because AMD was the first to make a "true" quad core.

 

Naples is going to be fucked with the number of interconnects it's going to have going on.

naples probably won't be made of quad cores CCXs (maybe 8-core CCX or something?)

also, server work doesn't really care about CCXs. intel's dual CPU motherboards have a similar performance overhead from dual CPUing (more overhead, acutally) and they still work just fine for servers.

[cj09beira]

24 minutes ago, Doobeedoo said:

Saw the G.Skill Ryzen certified memory and fastest is 3466MHz 2x8GB they list. Would like to see that running. Planning build on summer so I'd probably go with that.

Also I do wonder about BIOS updates for memory issues, how much will it differ. I'm sure current issues will be resolved so out of box it works fine, but what will be the maximum frequency it will be able to run in the end. Probably the above one, but we'll see.
Also, since desktop quad core si 2+2 between 2 CCXs potentially APUs that are quad core will be single CCX then. 

the thing is that it seems ryzens sub timings are too tight, so instead of running the 32 multiplier you need to use the 2933 multiplier and then increase the base clock

[cj09beira]

16 minutes ago, RadiatingLight said:

naples probably won't be made of quad cores CCXs (maybe 8-core CCX or something?)

also, server work doesn't really care about CCXs. intel's dual CPU motherboards have a similar performance overhead from dual CPUing (more overhead, acutally) and they still work just fine for servers.

its going to be 4 core ccxs they made them to have flexibility it would be stupid to make a new ccx just for servers 

[DocSwag]

55 minutes ago, AnonymousGuy said:

Oh good so they're going back to the Pentium D days where it was dual cores glued together, which was ironic because AMD was the first to make a "true" quad core.

 

Naples is going to be fucked with the number of interconnects it's going to have going on.

Professional workloads seem to be punished less by the infinity fabric than other workloads, so I don't think it'll be that bad. They showed one benchmark so far and it seems pretty promising, so I don't think it'll be too bad.

[leadeater]

2 hours ago, AnonymousGuy said:

Naples is going to be fucked with the number of interconnects it's going to have going on.

Naples uses an entirely different memory controller and we have no information on how CCXs are interconnected on that platform, Ryzen is a terrible reference point to try and make any judgement about Naples.

 

Also Naples is designed as a platform to host many PCIe accelerators (GPUs/FPGAs/ASICs etc), CPU performance while going to be absolutely fine isn't as big of a factor as you might think. One thing Ryzen does show us is that the CCX performance is actually very good, 8 of them (32 cores) will have extremely good performance.

 

1 hour ago, DocSwag said:

Professional workloads seem to be punished less by the infinity fabric than other workloads, so I don't think it'll be that bad. They showed one benchmark so far and it seems pretty promising, so I don't think it'll be too bad.

See comment above, Naples won't be using the Infinity Fabric, if it is (by name only) it's going to be substantially different.

[DocSwag]

4 minutes ago, leadeater said:

Naples uses an entirely different memory controller and we have no information on how CCXs are interconnected on that platform, Ryzen is a terrible reference point to try and make any judgement about Naples.

 

Also Naples is designed as a platform to host many PCIe accelerators (GPUs/FPGAs/ASICs etc), CPU performance while going to be absolutely fine isn't as big of a factor as you might think. One thing Ryzen does show us is that the CCX performance is actually very good, 8 of them (32 cores) will have extremely good performance.

 

See comment above, Naples won't be using the Infinity Fabric, if it is (by name only) it's going to be substantially different.

Hm yeah, though it's still gonna have some inter-die connection stuff going on. I recall that the 32 core CPU they will have is just two 16 core dies on the same substrate, so those are going to need a connection between them as well. I think I recall that the connection used on the motherboard between the two 32 core CPUs is based on the infinity fabric as well but I could be wrong about that.

[leadeater]

12 minutes ago, DocSwag said:

Hm yeah, though it's still gonna have some inter-die connection stuff going on. I recall that the 32 core CPU they will have is just two 16 core dies on the same substrate, so those are going to need a connection between them as well. I think I recall that the connection used on the motherboard between the two 32 core CPUs is based on the infinity fabric as well but I could be wrong about that.

Not sure about the internal die makeup, haven't really paid too much attention to that yet since it's too soon for me to trust any of the information .

 

Your correct the CPUs are linked by an Infinity Fabric (had to go look it up again). It's quite different from my understanding though but either way it uses PCie lanes in the CPUs to connect them together, 64 of them so that is a huge amount of bandwidth. My guess since I'm fairly sure it's based on Gen-Z tech that the Infinity Fabric is more of a communication protocol that can be used over many different transport mediums.

[DocSwag]

3 hours ago, leadeater said:

Not sure about the internal die makeup, haven't really paid too much attention to that yet since it's too soon for me to trust any of the information .

 

Your correct the CPUs are linked by an Infinity Fabric (had to go look it up again). It's quite different from my understanding though but either way it uses PCie lanes in the CPUs to connect them together, 64 of them so that is a huge amount of bandwidth. My guess since I'm fairly sure it's based on Gen-Z tech that the Infinity Fabric is more of a communication protocol that can be used over many different transport mediums.

Yeah, I remember seeing somewhere that it's something like each CPU has 128 lanes or something and they use 64 to connect to each other and the others for io. 

[leadeater]

1 hour ago, DocSwag said:

Yeah, I remember seeing somewhere that it's something like each CPU has 128 lanes or something and they use 64 to connect to each other and the others for io. 

Yep, it's rather weird in how they have a done it. A single Naples CPU has 128 usable PCIe lanes and dual Naples CPUs have 128 usable PCIe lanes, half in each processor get used for the interconnection of the CPUs.

[2FA]

11 minutes ago, leadeater said:

Yep, it's rather weird in how they have a done it. A single Naples CPU has 128 usable PCIe lanes and dual Naples CPUs have 128 usable PCIe lanes, half in each processor get used for the interconnection of the CPUs.

Ignoring the latency, does that mean you could do PCIe CPU expansion cards?

[leadeater]

7 minutes ago, DeadEyePsycho said:

Ignoring the latency, does that mean you could do PCIe CPU expansion cards?

A general purpose CPU, technically possible and is actually what is being done here with Naples just not in the way your asking. A x16 PCIe 3.0 slot is probably a little too slow to be all that useful and every CPU in the system needs to be connected in a full mesh which is why Naples is limited to dual socket. Three Naples CPUs would use every PCIe lane for the interconnect and none left over for I/O.

 

Latency isn't actually an issue, so long as the CPU is designed for it. Remember PCIe lanes are delivered directly from within the CPU die.

[Gich165]

On 3/16/2017 at 10:50 PM, RadiatingLight said:

intel actually has some undercover employees at AMD to mess up their chipset and memory controller so intel can still have some hidden advantages in the market.

according to my uncle's barber's drug dealer's friend who once went to a strip club owned by lisa su's cousin, intel actually put small devices embedded in the die of every Ryzen CPU which, when intel decides to, overload the CPU with 5 Volts and kills it. this way, intel always can remain the market leader. if they lose, they can just kill all of AMD.

Fuck Nvidia

What a rollercoaster of a comment. Wow 11/10

[MageTank]

13 hours ago, Kloaked said:

All of a sudden, tons of LTT members rush to Google to type in "CPU Infinity Fabric" so that they can argue about things that they read about on Wikipedia.

Then there is me, completely ignoring the logic behind the infinity fabric, and only seeing "can be improved by memory overclocking" lol. If they fix the IMC, I expect to see a world where people dial back CPU clocks just to get more out of their memory, instead of the other way around, lol. 

[Droidbot]

Just now, MageTank said:

Then there is me, completely ignoring the logic behind the infinity fabric, and only seeing "can be improved by memory overclocking" lol. If they fix the IMC, I expect to see a world where people dial back CPU clocks just to get more out of their memory, instead of the other way around, lol. 

Running a 7 1700 at 2.5Ghz undervolted to save voltage to push into the IMC

3466Mhz memory, or possibly even 3600Mhz. 

 

50+GB/s Notbadman

[MageTank]

Just now, Droidbot said:

Running a 7 1700 at 2.5Ghz undervolted to save voltage to push into the IMC

3466Mhz memory, or possibly even 3600Mhz. 

 

50+GB/s Notbadman

Part of the reason I run my CPU at stock, is because my aggressive memory overclocks add quite a bit of heat to the CPU package. Difference between JEDEC 2133 and my 3600 C14-14-14-28-2 is about 12C under AVX load, just changing memory profiles. Add an OC on top of that, and it's curtains for my poor ITX box, lol. 

[Droidbot]

Just now, MageTank said:

Part of the reason I run my CPU at stock, is because my aggressive memory overclocks add quite a bit of heat to the CPU package. Difference between JEDEC 2133 and my 3600 C14-14-14-28-2 is about 12C under AVX load, just changing memory profiles. Add an OC on top of that, and it's curtains for my poor ITX box, lol. 

Poor IMC.. I run my CPU OC'd but my memory is only at 1600Mhz anyway and I can't be screwed manually OCing for the small amount of actual performance I get 

[MageTank]

3 hours ago, ONOTech said:

So your theory here is that the timings are connected to the Infinity Fabric - and if you mess with them you could potentially entirely screw up the connection between CCXs? And that's why AMD locked most memory modification settings?

 

You definitely did not lie, it's a reach, but possible. I know I'm beating at a dead horse by saying this, but could it be simply because it's a brand new architecture and they're still working through the kinks and bugs? Could it be the RAM kits themselves? Although it's few and far between, some RAM modules can run 3200+ MHz on an AM4 board with the right settings. 

It very well could be the kits. Understand, different IC's (Hynix, Samsung, Micron, Elpida, etc) all behave differently when it comes to tertiary timings. This is why AMD are recommending Samsung B-Die to achieve those 3200mhz clock speeds. Their IMC simply prefers Samsung (it preferred Elpida in the past, and Samsung is very similar to Elpida in that regard). AMD has always had a touchy relationship with Hynix IC's, so I have no doubt the ram itself is playing a fairly decent part in this. What worries me, is the 2DPC issues and multi-rank issues. 

 

You see, with tertiary timings, you can actually fix 2DPC issues and multi-rank issues. These timings use _DD and _DR suffixes respectively. By loosening these timings, you ease the stress that 2DPC and multi-rank puts on the IMC. The tradeoff for this stability, is performance. Reducing the _DR timings will reduce the impact of Rank Interleaving, which impacts your memory copy speed. Reducing the _DD timings will impact your reads and writes, but not by much at all. In fact, it's very minimal compared to _SG. 

 

I should seriously find some free time to finish my ram guide. Either that, or pawn my information off on someone that has the time to do it, lol. 

[NumLock21]

21 hours ago, Kloaked said:

All of a sudden, tons of LTT members rush to Google to type in "CPU Infinity Fabric" so that they can argue about things that they read about on Wikipedia.

And probably thought you can make one with a sewing machine.

 

[Techstorm970]

On 3/16/2017 at 8:52 PM, deXxterlab97 said:

that source is more reputable than wcftech

Or as I like to call them, WTFtech. 

[MyName13]

Has anyone tested ryzen with single channel ram?

[MageTank]

30 minutes ago, MyName13 said:

Has anyone tested ryzen with single channel ram?

That is actually a very smart question. It would confirm whether or not the IF is tied to raw bandwidth, or just the clock speed itself. I'll pass this question along to some friends with Ryzen CPU's. Thanks for the suggestion.

[79wjd]

4 hours ago, MageTank said:

That is actually a very smart question. It would confirm whether or not the IF is tied to raw bandwidth, or just the clock speed itself. I'll pass this question along to some friends with Ryzen CPU's. Thanks for the suggestion.

Let me know what the results are.