AMD Ryzen Chips 10% Smaller When Compared to Intel Skylake Dies

[Coaxialgamer]

Quote

In a separate paper, AMD said its upcoming Zen x86 core fits into a 10 percent smaller die area than Intel’s currently shipping second-generation 14nm processor. Analysts and even Intel engineers in the session said the Zen core is clearly competitive though many confidential variables will determine whether the die advantage translates into lower cost for AMD.

 

EEtimes: The paper detailed techniques AMD used to reduce switching capacitance by 15 percent compared to its existing chips.

 

For example, Zen marked AMD’s first use of a metal-insulator-metal capacitor which helped lower operating voltages and provide greater per-core voltage and frequency control.

 

Engineers tracked on a weekly basis power benchmarks on high activity regions for more than a year to reduce switching capacitance. The company now has two eight-core designs running with simultaneous multithreading at 3.4 GHz.

 

One of my primary concerns with ryzen is die size,  as it largely determines the economics of the chip.  

A larger die is more expensive to produce,  and is also harder to manufacture than a small die.  

A larger die can also mean higher heat and power consumption. 

In fact,  a large die size was one of the many problems with AMD's previous architecture,  bulldozer (316mm²).

Hopefully this turns out to be true in the real world.  If that is the case,  AMD has themselves a real winner of an architecture,  especially considering that the 14nm lpp process they use is less dense than intel's. 

 

Source :http://www.guru3d.com/news-story/amd-ryzen-chips-10-smaller-when-compared-to-intel-skylake-dies.html

 

http://www.eetimes.com/document.asp?doc_id=1331317&page_number=2

[vanished]

lol "Competitor" .... couldn't possibly be Intel 

[themctipers]

inb4 cannonlake destroys zen

[Coaxialgamer]

Just now, Ryan_Vickers said:

lol "Competitor" .... couldn't possibly be Intel 

Just like in advertisements for detergent! 

[Majestic]

6 minutes ago, Ryan_Vickers said:

lol "Competitor" .... couldn't possibly be Intel 

It's def. Qualcomm 

[johnt]

11 minutes ago, Coaxialgamer said:

Just like in advertisements for detergent! 

Except there's actually more than two detergents lol

[anticeon]

I hope really Zen serious problem. not just for Internet Cafe CPU

[vanished]

Do we know this news is real and directly from AMD?  Because if not, all we have is a screenshot of a spreadsheet anyone would have made in 2 minutes with fake numbers for hype.

[SuperShires]

7 minutes ago, anticeon said:

I hope really Zen serious problem. not just for Internet Cafe CPU

Yes.

[Coaxialgamer]

22 minutes ago, Ryan_Vickers said:

Do we know this news is real and directly from AMD?  Because if not, all we have is a screenshot of a spreadsheet anyone would have made in 2 minutes with fake numbers for hype.

Supposedly this from ISSCC 2017, which is happening right now.  Can't find an exact transcript,  but EEtimes isn't WCCFtech either. 

[manikyath]

51 minutes ago, Ryan_Vickers said:

lol "Competitor" .... couldn't possibly be Intel 

i actually think that to some degree they're required to do that by law.

[HelplmChoking]

So AMD looked at the Skylake stats, and basically said "we will make that, but with every number a bit bigger".

Also, die size isn't that important but will AMD use a proper substrate that doesn't bend with simple gravity, and will they use proper thermal materials in the IHC?

[manikyath]

so.. i'm just thinking, is this a zen chip with or without iGPU?

[patrickjp93]

The only die we have is an 8-core, and the 6900K is a cut-down 10-core die. Seriously people, think...

 

And even if this is a quad-core module, Intel has the iGPU included and AMD doesn't. Either way, huge density DISadvantage for AMD.

[patrickjp93]

5 minutes ago, Rangaman42 said:

So AMD looked at the Skylake stats, and basically said "we will make that, but with every number a bit bigger".

Also, die size isn't that important but will AMD use a proper substrate that doesn't bend with simple gravity, and will they use proper thermal materials in the IHC?

The substrate bends have all been found to be caused with abusive mounting force such as with a power drill. The reports stopped after the first few for exactly this reason. It's not an actual problem.

[WereCat]

38 minutes ago, anticeon said:

I hope really Zen serious problem. not just for Internet Cafe CPU

You english very yes!

 

Isn't it smaller because there will be no iGPU yet?

[HelplmChoking]

1 minute ago, patrickjp93 said:

The substrate bends have all been found to be caused with abusive mounting force such as with a power drill. The reports stopped after the first few for exactly this reason. It's not an actual problem.

 

Oh good, glad that wasn't an issue, that just leaves Intel's crappy IHC.

[Guest Kloaked]

It's not the size that matters.

[leadeater]

31 minutes ago, patrickjp93 said:

The only die we have is an 8-core, and the 6900K is a cut-down 10-core die. Seriously people, think...

 

And even if this is a quad-core module, Intel has the iGPU included and AMD doesn't. Either way, huge density DISadvantage for AMD.

What's been shown isn't the total package area, it's the internal die makeup. Ryzen uses 4 cores per module, CCX (CPU Complex), and Intel uses a similar internal design makeup however I'm not sure if their's are in 4 core groupings like AMD's.

 

This is actually a massive density win for AMD as they are getting 4 cores with twice the L2 cache and same L3 cache in a smaller area. If anyone actually thought the total package area was 44mm² or 49mm² for either of them then they are mistaken,

 

Ryzen total package area will also be smaller than Intel's enthusiast lineup as the memory controller is much smaller, dual channel vs quad channel, and the above mentioned CCX size. 

 

Edit:

Also forgot another big die area usage, Ryzen has less PCIe lanes than Intel-E.

[patrickjp93]

20 minutes ago, Rangaman42 said:

Oh good, glad that wasn't an issue, that just leaves Intel's crappy IHC.

The paste isn't the problem either. Both Intel and AMD use Dow Corning between the die and IHS (see AMD APUs). The problem is the glue Intel uses is so viscous the spacing between die and IHS is inconsistent and can be too large. That's the single biggest contributing factor to the temperatures. Just removing the glue and applying Dow Corning reduces temps by 15-20 degrees. The extra 5 CLU gets you is great, but you have to reapply CLU every 12 months or so.

[patrickjp93]

2 minutes ago, leadeater said:

What's been shown isn't the total package area, it's the internal die makeup. Ryzen uses 4 cores per module, CCX (CPU Complex), and Intel uses a similar internal design makeup however I'm not sure if their's are in 4 core groupings like AMD's.

 

This is actually a massive density win for AMD as they are getting 4 cores with twice the L2 cache and same L3 cache in a smaller area. If anyone actually thought the total package area was 44mm² or 49mm² for either of them then they are mistaken,

 

Ryzen total package area will also be smaller than Intel's enthusiast lineup as the memory controller is much smaller, dual channel vs quad channel, and the above mentioned CCX size. 

I'm sorry but that's ridiculous. AMD is cherry picking components to compare. Anandtech will clear this up in short order after launch.

[leadeater]

Just now, patrickjp93 said:

I'm sorry but that's ridiculous. AMD is cherry picking components to compare. Anandtech will clear this up in short order after launch.

Well it's not ridiculous it's true, but die area difference is hardly actually relevant to anything so why does it matter? It only matters to AMD in regards to production cost or more correctly dies per wafer. For us it's "nice spreadsheet of numbers you have there, why do I care?".

[Curufinwe_wins]

8 minutes ago, leadeater said:

Well it's not ridiculous it's true, but die area difference is hardly actually relevant to anything so why does it matter? It only matters to AMD in regards to production cost or more correctly dies per wafer. For us it's "nice spreadsheet of numbers you have there, why do I care?".

Actually it is pretty terribly discouraging information if true. IMHO

 

Look at the transistor standard size..... The Ryzen chips have to be far FAR less complex (and probably therefor worse at HPC type loads) in order to come in at the same total die size.

 

Obviously # transistors is no where near an all-encompassing stat for performance, but the fact of the matter is that Intel doesn't waste die space, so if AMD has a smaller die, AND has a provably less dense process, they simply CANNOT house the same capabilities [on silicon].

 

[cj09beira]

6 minutes ago, Curufinwe_wins said:

Actually it is pretty terribly discouraging information if true. IMHO

 

Look at the transistor standard size..... The Ryzen chips have to be far FAR less complex (and probably therefor worse at HPC type loads) in order to come in at the same total die size.

 

Obviously # transistors is no where near an all-encompassing stat for performance, but the fact of the matter is that Intel doesn't waste die space, so if AMD has a smaller die, and has a provably less dense process, they simply CANNOT house the same capabilities.

 

its more complicated than that as you can have the same design use more or less transistors depending on what characteristics the cpu should have 

edit:

and we don't know if the igpu is being counted or not 

[Curufinwe_wins]

5 minutes ago, cj09beira said:

its more complicated than that as you can have the same design use more or less transistors depending on what characteristics the cpu should have 

It isn't perfect, but it actually is pretty damn close to being right. KNL/Atom is fewer transistors per core because they are simpler, weaker, shallower cores. Same with ARM (higher performance cores means bigger). Every feature and process and register you put on a CPU means transistors being used, and it is quite foolish to assume that AMD has the capability to deliver all the same features (ALL, not just the standard stuff for normal consumer loads that aren't properly optimized) and the same performance at the same clocks with 10% reduction in area, WHILE using a process that takes 37% more space for a very well optimized 6T cell.

 

It is just not a realistic belief.