Skyscraper-style chip design boosts performance 1,000-fold

[Terry]

For decades, engineers have designed computer systems with processors and memory chips laid out like single-story structures in a suburb. Wires connect these chips like streets, carrying digital traffic between the proce

ssors that compute data and the memory chips that store it.

 

But suburban-style layouts create long commutes and regular traffic jams in electronic circuits, wasting time and energy.

That is why researchers from three other universities are working with Stanford engineers, including Associate Professor Subhasish Mitra and Professor H.-S. Philip Wong, to create a revolutionary new high-rise architecture for computing.

In Rebooting Computing, a special issue of the IEEE Computer journal, the team describes its new approach as Nano-Engineered Computing Systems Technology, or N3XT.

N3XT will break data bottlenecks by integrating processors and memory like floors in a skyscraper and by connecting these components with millions of "vias," which play the role of tiny electronic elevators. The N3XT high-rise approach will move more data, much faster, using far less energy, than would be possible using low-rise circuits.

"We have assembled a group of top thinkers and advanced technologies to create a platform that can meet the computing demands of the future," Mitra said.

Shifting electronics from a low-rise to a high-rise architecture will demand huge investments from industry – and the promise of big payoffs for making the switch.

"When you combine higher speed with lower energy use, N3XT systems outperform conventional approaches by a factor of a thousand," Wong said.

To enable these advances, the N3XT team uses new nano-materials that allow its designs to do what can't be done with silicon – build high-rise computer circuits.

"With N3XT the whole is indeed greater than the sum of its parts," said co-author and Stanford electrical engineering Professor Kunle Olukotun, who is helping optimize how software and hardware interact.

I guess we will see if this plays out, cooling is going to be interesting can't seem to find anything that specifies thermals.

http://phys.org/news/2015-12-skyscraper-style-chip-boosts-fold.html

[skyress3000]

Looks interesting - maybe more relevant to consumers than quantum computers?

[thekeemo]

Looks interesting - maybe more relevant to consumers than quantum computers?

Absolutely 

[The_Stig]

Cooling wont be that interesting. Instead of flat bases on the coolers, they will just have a square-shaped hole.

[HalGameGuru]

Need to get some more article info in here, but its super interesting, it builds off of the carbon nanotube transistors we've had reported on here a while back. Utilizing them to allow striated multi-layered construction of memory and processing with "electron elevator" vias connecting the layers together, if we can get these things efficient and tiny enough you could have whole systems designed around this build style. imagine an entire Intel i7 system the size of a deck of cards, CPU, GPU, RAM, interconnects and I/O. Running off of the same amount of power as a current gen cell phone.

[AresKrieger]

@Terry interesting, but you need to quote part of the article (section rule) may I suggest posting that image and maybe the first block of text

[dizmo]

You'd think they would have thought of something like this sooner. It just seems logical.

[AresKrieger]

You'd think they would have thought of something like this sooner. It just seems logical.

Same thing could have been said about 3D nand, I suspect new chip manufacturing processes were the hold up, not the idea itself

[Terry]

@Terry interesting, but you need to quote part of the article (section rule) may I suggest posting that image and maybe the first block of text

Sorry, i posted it from my phone most of the functions aren't there, done now.

[AresKrieger]

Sorry, i posted it from my phone most of the functions aren't there, done now.

All good I was just giving a heads up before a mod told you

[carolkarine]

... How would a high powered version of this be cooled?

[Guest Kloaked]

You'd think they would have thought of something like this sooner. It just seems logical.

 

They may have thought about it for years and done on-paper stuff, but are only just now getting around to getting it to actually work is my guess.

 

There's plenty of other stuff that happens like this where you're like "Why wasn't it made like THIS in the first place???".

[Xorbot]

Feels like someone could make a video game out of this, and call it Sim Chip.

[Eroda]

soo this was kinda right???

 

[RagnarokDel]

... How would a high powered version of this be cooled?

integrated heatpipes in the design or just use multiphase.

[Bensemus]

I though there was a post on here a while ago about some people who etched water channels directly into the chip. They could use that kind of tech to cool down the stack.

[HalGameGuru]

Don't forget this design is not the traditional silicon wafer paradigm. The entire thing will be lower voltage, far more efficient, and the changes in physical architecture will reduce the heat creation we would expect to see.

[captain cactus]

Soooo....... Like HBM but for an entire CPU/GPU/SoC?

 

Neat.

[deviant88]

If cooling werent an issue at GHZ frequencies they would have done this a long time ago, we are still fighting with thermal limits, leaks and probably some production problems

But anyway lately shrinking stuff is starting to show its limits and everything seems to be going up from now, 3D nand, HBM stack, skyscraper chips we will keep seeing these, but so far it has been possible only for memory storage since they need less mhz and cooling, i doubt we will see such a cpu with traditional silicon, maybe in the future with graphite + skyscraper for 10k-fold performance.

[Sidiox]

I'm fairly sure Intel has been trying to do this for ages. But since we are also seeing HBM I'm fairly confident we'll see this in the near future.

[Stefan1024]

If you give the engineers 3 instead of 2 dimensions to play with sure you get a better result. Just look at 3d crosspoint memory.

However the cost will go up significantly in the first period and will eventually come back again when it's ready for mass production with good yields.

[CommandMan7]

As for the potential for cooling issues, I'd hope that due to the increased space, the IPC could be boosted to a level that allows for substantially lower clock speeds, maybe even as low as single digit Mhz's. If they end up stacking it, say 1000 levels high, and you could be getting skylake performance @ 4 Mhz. Latency would be a problem though, maybe get the cores to run their cores slightly out of sync on clockspeeds so the effective clockspeed is the number of cores times actual clockspeed?

[Stefan1024]

As for the potential for cooling issues, I'd hope that due to the increased space, the IPC could be boosted to a level that allows for substantially lower clock speeds, maybe even as low as single digit Mhz's. If they end up stacking it, say 1000 levels high, and you could be getting skylake performance @ 4 Mhz. Latency would be a problem though, maybe get the cores to run their cores slightly out of sync on clockspeeds so the effective clockspeed is the number of cores times actual clockspeed?

You head into the right direction, but you don't have to go that low. You would save significant power even at 500-1000 MHz.

[That Norwegian Guy]

Alright I'm done with this forum for tech news. Three OPs today who didn't set their text colour to automatic.

LTT does nothing about the text issue.

Word isn't spreading, or people don't give a shit, they just copy/paste and move on to the next.

RIP night theme this forum section.

[samcool55]

If cooling werent an issue at GHZ frequencies they would have done this a long time ago, we are still fighting with thermal limits, leaks and probably some production problems

But anyway lately shrinking stuff is starting to show its limits and everything seems to be going up from now, 3D nand, HBM stack, skyscraper chips we will keep seeing these, but so far it has been possible only for memory storage since they need less mhz and cooling, i doubt we will see such a cpu with traditional silicon, maybe in the future with graphite + skyscraper for 10k-fold performance.

Well i know they have showed a possible solution. Small channels where water can flow through to cool it off. Yes you still need a rad and such things but it's just a cpu block squished between the cpu layers instead being on top of everything.