I *JUST* upgraded.. I HATE it when this happens…

[AdamFromLTT]

Crucial just sent us their new T700 SSD and thanks to the power of PCIe Gen 5 this very well maybe the fastest NVMe SSD on the planet. So how fast does it go? And should you consider one for your next build?
 

 

[Zephyrmoth]

Pretty certain Linus mixed up "Final Fantasy 14" and the actual results when he was recording bc those numbers for Endwalker look like a 16% improvement just from napkin math and he did call it "FInal Fantasy: Endwalker" without the number.

[GeorgeMKane]

Cool video and very informative, but I think I'll stick with the 980 Pro for my next build. Don't need the Mach 6 from Speed Racer just yet. 

 

 

[acters]

Can someone from LTT team tells us the reasoning for setting the CrystalDiskMark settings to use 1 thread? performance is better from setting higher thread counts. Are we certain that you are not being CPU/RAM speed limited? is it because one thread is more realistic in file transfer scenarios vs multithreaded scenarios? does limiting threads also limits the amount of PCIE lanes in use? I feel like there is a lot of potential testing LTT labs needs to do

 

Source from another website claiming your testing is UNREALISTIC https://portal.nutanix.com/page/documents/kbs/details?targetId=kA07V000000LWkcSAG#:~:text=All four of the default tests are single-threaded%2C which does not show a realistic I/O profile for the vast majority of workloads as most modern applications are multi-threaded.

[spaghet rat]

why does the info in the video say the 13700k only has 8 cores when it has 16? @AdamFromLTTis this a typo or am i missing something?

[XNOR]

4 hours ago, acters said:

Can someone from LTT team tells us the reasoning for setting the CrystalDiskMark settings to use 1 thread? performance is better from setting higher thread counts. Are we certain that you are not being CPU/RAM speed limited? is it because one thread is more realistic in file transfer scenarios vs multithreaded scenarios? does limiting threads also limits the amount of PCIE lanes in use? I feel like there is a lot of potential testing LTT labs needs to do

 

Source from another website claiming your testing is UNREALISTIC https://portal.nutanix.com/page/documents/kbs/details?targetId=kA07V000000LWkcSAG#:~:text=All four of the default tests are single-threaded%2C which does not show a realistic I/O profile for the vast majority of workloads as most modern applications are multi-threaded.

Testing with a single thread is definitely the default amongst reviewers. Setting the number of threads to something higher, like 32, yields a very different result. It'd be interesting to see whether the relative performance holds up between the two SSDs when the threads are changed.

 

Quick and dirty 1 versus 32 thread tests:

 

 

[XNOR]

4 hours ago, McrP87 said:

why does the info in the video say the 13700k only has 8 cores when it has 16? @AdamFromLTTis this a typo or am i missing something?

Timestamp?

[acters]

1 hour ago, XNOR said:

Testing with a single thread is definitely the default amongst reviewers. Setting the number of threads to something higher, like 32, yields a very different result. It'd be interesting to see whether the relative performance holds up between the two SSDs when the threads are changed.

 

Quick and dirty 1 versus 32 thread tests:

 

 

using your settings

Here are mine:

and

 

But the article I linked said to match thread to the CPU's so here is mine with 12:

Notice the strangeness that write 4kQ32 and read 4kQ1 are the only that change significantly? multiple tries similar results

 

and lastly following the article linked earlier had recommended settings:(kept threads at 12 because I have a 12 threaded CPU)

[spaghet rat]

9 hours ago, XNOR said:

Timestamp?

12:01

[Nystemy]

This is incorrect:

 

I see that this is ripped straight from Wikipedia's article on the PCIe slot: https://en.wikipedia.org/wiki/PCI_Express#Pinout

But missing the all important fact that the fist 22 pins is power and SMBus/JTAG. The next 12 pins contains the first 1 PCIe lane.
Yes, that is 36 pins for 1 lane, not 18.

The trend then continues. _{(the editor/writer missed the fact that there were an A and B column for each side of the connector.)}

However, the M.2 connector has a completely different pinout.

But. This is still "incorrect" as far as talking about CPUs and PCIe lane count goes in terms of socket pin count.
On a socket, a PCIe typically uses 6-8 pins per lane. Depending on how the CPU vendor has decided to isolate the differential pairs from each other.
_{(in general, all high speed differential pairs will have 1-2 ground pins surrounding them for isolation on a socket/connector, regardless of protocol.)}

[acters]

8 hours ago, Nystemy said:

This is incorrect:

 

I see that this is ripped straight from Wikipedia's article on the PCIe slot: https://en.wikipedia.org/wiki/PCI_Express#Pinout

But missing the all important fact that the fist 22 pins is power and SMBus/JTAG. The next 12 pins contains the first 1 PCIe lane.
Yes, that is 36 pins for 1 lane, not 18.

The trend then continues. _{(the editor/writer missed the fact that there were an A and B column for each side of the connector.)}

However, the M.2 connector has a completely different pinout.

But. This is still "incorrect" as far as talking about CPUs and PCIe lane count goes in terms of socket pin count.
On a socket, a PCIe typically uses 6-8 pins per lane. Depending on how the CPU vendor has decided to isolate the differential pairs from each other.
_{(in general, all high speed differential pairs will have 1-2 ground pins surrounding them for isolation on a socket/connector, regardless of protocol.)}

As a hardcore tech enthusiast, I appreciate this community. My biggest gripe with storage performance and specifications, the underlying tech is never explored or explained. This video states whether or not Gen 5 NVME drives are worth it, while never clearly testing these drives and moving the sponsoring advertising claims with no real substance for tech enthusiasts to use. This type of content undercuts the mission LTT claims at keeping manufacturers honest. Disappointed

[GodAtum]

I'm a bit confused with the plane analogy. Please explain to my stupid brain why cant they just make SSDs have 2 aisles (either sides of the 3 seats)?

[zENjA]

Maybe I'm oldschool, but I think "more speed" is not everything.

I would love to step down my PCIe Nx4x NVMe U.2 Server to an PCIe 5 1x and then add 36x SSDs in 1U.

or it's just me, who is dealing with servers all day

[Blade654]

On 3/20/2023 at 6:55 AM, GodAtum said:

I'm a bit confused with the plane analogy. Please explain to my stupid brain why cant they just make SSDs have 2 aisles (either sides of the 3 seats)?

You could but there is no space for the extra aisle. You'd have to remove a seat from each row to make room for it. This would reduce capacity and effectively increase cost since there are less seats to make money off of.

 

Also in reality the rows have thousands of seats and they do make a similar trade off between adding more aisles and cost.