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Are there PCIe lane issues using 2x NVMe drives?

Am I going to have performance degradation due to NVMe / PCIe lane issues on my new system?

 

Will adding, for example, a PCIe x1 peripheral card wreck my NVMe performance due to resource sharing?

 

I never thought about PCIe lane resources until recently and now I'm getting flashbacks to the IRQ days!  

I built my new machine over time to do modest video editing, Photoshop, and some data crunching (Access databases, etc). I don't really game much.  Right now, everything works fine, but I haven't benchmarked anything.

 

ASUS TUF x570-Plus mobo

AMD Ryzen 5 3600

4x 8GB Crucial Ballistix 3600

XFX RX 590 Fatboy 8GB (used - - best I could do during the GPU price hike)

1x Crucial P5 500GB NVMe M.2 SSD for boot/app

1x Crucial P5+ 500GB NVMe M.2 SSD for scratch/cache*

2x Seagate Iron Wolf Pro 4TB HDD (CMR) in RAID for long-term storage

 

*The P5+ wasn't available when I first built the machine. The plan is to eventually migrate the P5 to a secondary machine. The P5+ went to scratch because I understood that to be the most speed-sensitive storage need.

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A x4/x2 m.2 won't affect anything. Those extra 2 lanes just won't be used.

 

The x1 slots on the board will be connected to the chipset, so they won't affect any other devices.

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5 minutes ago, Electronics Wizardy said:

A x4/x2 m.2 won't affect anything. Those extra 2 lanes just won't be used.

 

The x1 slots on the board will be connected to the chipset, so they won't affect any other devices.

Am I misunderstanding the lane system?  My thinking was... 

24 lanes on Ryzen 5 3600

4 go to chipset

16 go to GPU

That leaves x4.  If each M.2 drive takes x4 (one is Gen 3 and one is Gen 4), aren't i running into resource sharing?

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4 minutes ago, MAXBattle said:

Am I misunderstanding the lane system?  My thinking was... 

24 lanes on Ryzen 5 3600

4 go to chipset

16 go to GPU

That leaves x4.  If each M.2 drive takes x4 (one is Gen 3 and one is Gen 4), aren't i running into resource sharing?

The gen 4 pulls from the direct lanes (x4 as you mentioned)

The second M.2 pulls from the chipset which has like 20 lanes but "bottlenecks" down to the x4 lanes up to the CPU.

Current Network Layout:

Current Build Log/PC:

Prior Build Log/PC:

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