Motherboard PCIe connections

[Chiyawa]

Hi,

 

Well, I'm curious on how does all the components (such as USB ports, PCIe slots) route to the chipset and CPU. My curiosity actually begins from my previous post.

 

Anyway, does anyone have any idea on how the components routes? I try to understand how all this things connected to, how much PCIe lanes are assigned to each devices, and how the devices route configured.

 

So far what I know (at least for Gigabyte X570 Aorus Pro WiFi v1.0 (no thunderbolt support):

X570 has 20 PCIe lanes.

4 lanes link to the CPU

4 lanes link to PCIe x4 slot

4 lanes link to M2 slot

1 lane links to PCIe x1 slot

1 lane links to another PCIe x1 slot

1 lane links to Intel I211 Ethernet controller

1 lane links to Intel WiFi AX200

I'm not sure where another 4 lanes go, probably turned into 4x SATA.

 

Now, what even confused me is that HWiNFO reported something I couldn't fathom. You can check the .csv file, but I summarised over here:

8 lanes link to CPU (currently running on 4 lanes)

4 lanes link to PCIe x4 slot (which is populated)

1 lane links to Intel I211 Ethernet Controller

1 lane links to Intel WiFi AX200

16 lanes link to 2 XHCI USB controllers

16 lanes link to SATA controller - 2 SATA port

16 lanes link to another SATA controller - 4 SATA port

The M2 slot and PCIe x1 slots are hidden from the detection, probably no devices are connected to the slots.

 

So, I'm getting confused. Can anyone clarify me of this? It's strange to see so many lanes pop up of nowhere, because I clearly remember AMD clarifies that the chipset has 5x x4 PCIe PHY (which total to 20 lanes) from this picture I get from AnadTech:

I tried to search the Internet about the Bus allocation, but I can't seems to find a proper explanation for this... reports. Any help will be appreciated.

 

Regards,

Chiyawa.

 

P.S.: I'm running HWiNFO 6.24-4120

DESKTOP-OB74C2F.CSV

[The_russian]

I am by no means an expert on this topic, but here's a picture that might make a little more sense:

 

 

If I understand it correctly, HWInfo doesn't make a distinction between lanes from the CPU and lanes from the chipset, which is why it adds up to more than it looks like it should. There are 24 total PCIe lanes from the CPU with 16 lanes for the graphics card, 4 for storage (m.2), and 4 for the chipset. The chipset then has 16 PCIe lanes that it uses for PCIe slots, m.2 slots, and SATA. 

 

If I said something wrong, someone feel free to correct me, because like I said I am no expert in this. 

[mariushm]

CPU has 24 pci-e lanes :

16 go to graphics : 1 pci-e x16 or 2 slots x8 each

4 go to m.2 connector

4 go to chipset

 

Chipset creates additional pci-e lanes, up to 12 on x570 but like picture above shows ... 8 are strictly pci-e lanes, the other 4 are choice between having pci-e lanes for slots, pci-e lanes for m.2 nvme connector, or disabling the pci-e lanes to get more sata ports

 

[Chiyawa]

2 minutes ago, The_russian said:

HWInfo doesn't make a distinction between lanes from the CPU and lanes from the chipset, which is why it adds up to more than it looks like it should.

Well, actually it kinda does, as this is all in the AMD 500 series chipset.

 

Here's the screenshot:

[Chiyawa]

1 minute ago, mariushm said:

Chipset creates additional pci-e lanes, up to 12 on x570 but like picture above shows ... 8 are strictly pci-e lanes, the other 4 are choice between having pci-e lanes for slots, pci-e lanes for m.2 nvme connector, or disabling the pci-e lanes to get more sata ports

Yes, but now this really confused me. If you look at what HWiNFO report, you'll see that the 2 USB XHCI controllers uses PCIe x16, and 2 SATA controllers each uses PCIe x16. Those add up to 42 lanes, which is a bit crazy.

[mariushm]

Those are strictly inside the chipset, not available outside the chip, there's no pins to route those pci-e lanes to slots or m.2 connectors or whatever.

 

It's like the HSIO stuff inside intel chipsets , where single or groups or hsio links can connect things inside chipset.

[Chiyawa]

Just now, mariushm said:

Those are strictly inside the chipset, not available outside the chip, there's no pins to route those pci-e lanes to slots or m.2 connectors or whatever.

 

It's like the HSIO stuff inside intel chipsets , where single or groups or hsio links can connect things inside chipset.

I see.

 

This... However intrigues me. I mean, why would a SATA controllers need so many PCIe lanes when they only support 2 ports of SATA devices?

 

But more importantly, is HWiNFO reporting correct PCIe lane usage for each devices?

 

There's an article claimed the chipset actually has 40 PCIe lanes! Here's the link: https://www.techpowerup.com/255008/amd-x570-chipset-to-feature-40-pcie-4-0-lanes

This is the best article I could find, but somehow... Something is amiss.

 

So, we know that 4 PCIe lanes go to CPU, 16 lanes is usable, that means another 20 lanes for SATA and USB XHCI controllers? And even so, they don't really need that high bandwidth, right? The chipset supports up to 8x USB 3.2 Gen 2 ports (which is 80Gbps total), 4 USB 2.0 (which is about 2Gbps total) and 4 SATA ports (24Gbps total), so its total up to 106Gbps*. PCIe gen 4 x16 provided 252.06Gbps, even x8 provides 126Gbps (unless they are using Gen3 PCIe, they would then need x16 lanes, but according to HWiNFO, they are running Gen4 PCIe)! Well, I'm not sure, but I'm going to dig more into this. Just hope that I don't dig myself into my own grave...

 

*Assuming the default X570 configuration

[mariushm]

1 hour ago, Chiyawa said:

There's an article claimed the chipset actually has 40 PCIe lanes! Here's the link: https://www.techpowerup.com/255008/amd-x570-chipset-to-feature-40-pcie-4-0-lanes

This is the best article I could find, but somehow... Something is amiss.

 

So, we know that 4 PCIe lanes go to CPU, 16 lanes is usable, that means another 20 lanes for SATA and USB XHCI controllers? And even so, they don't really need that high bandwidth, right? The chipset supports up to 8x USB 3.2 Gen 2 ports (which is 80Gbps total), 4 USB 2.0 (which is about 2Gbps total) and 4 SATA ports (24Gbps total), so its total up to 106Gbps*. PCIe gen 4 x16 provided 252.06Gbps, even x8 provides 126Gbps (unless they are using Gen3 PCIe, they would then need x16 lanes, but according to HWiNFO, they are running Gen4 PCIe)! Well, I'm not sure, but I'm going to dig more into this. Just hope that I don't dig myself into my own grave...

 

*Assuming the default X570 configuration

No, the 40 pci-e lanes was just some confusion, where people were adding the pci-e lanes created by the cpu with the pci-e lanes created by the chipset and got to 40.

 

The processors create a bunch of pci-e lanes, up to 24 pci-e lanes for the socket AM4 processors. However, 4 of those are always used to connect the chipset to the processor, leaving 20 pci-e lanes from the processor to be used for things.

16 out of those 20 are supposed to be used for video graphics, for the first pci-e x16 and depending on the chipset, these 16 may be split into 2  x8 slots (B450 can't do it, x470 can do it, x570 can do it, the B550 probably won't be able to do it)

The rest of 4 pci-e lanes are recommended to be used for the first m.2 connector, but it's up to motherboard manufacturer if they use them for that - majority of them use it like that.

 

Think of the chipset like a network switch with 24-48 1gbps ports and an incoming 10gbps port which connects the switch to the outside world (the WAN port).

The 10gbps port in this analogy is the pci-e x4 connection to the cpu, it's always locked to the cpu.

The chipset takes this x4 connection  (up to around 4 GB/s in both directions) and has a pci-e controller inside which creates maybe 24 or 32 pci-e lanes, but only 8 or 12 pci-e lanes are actually available outside the chipset.

 

For SATA, my guess is they're using 4 pci-e lanes for each group of 4 sata connectors. The maximum bandwidth of a single SATA port is around 560 MB/s.

Keep in mind that they just licensed the sata and usb controllers from Asmedia, and I think they were pci-e 3.0 only, so inside the chipset I suspect the connections to the usb and sata controllers are pci-e 3.0, which means each pci-e lane inside chipset  will do a maximum of 970 MB/s, or around 950 MB/s after overhead and other stuff. 

As a single sata port can do max 560 MB/s, most 2 port sata controllers use a single pci-e lane... if a single port is heavily used, it can do the 560 MB/s, if you use 2 ports at same time you get around 450 MB/s max on each port.

As you can see in the picture, there's basically 2 separate sata controllers in the x570 chipset, each with 4 sata ports. So, a minimum of 2 pci-e lanes would be needed, so I can see why they just went with 4 pci-e lanes for each sata controller.

 

I think you're making a confusion about what it says in the picture... you're seeing sata controller each on pci-e x16 but that doesn't really mean each controller gets 16 pci-e lanes... it's not that, it's kind of a multiplexing, virtual thing (each gets some time on the cable)

 

[Chiyawa]

@mariushm

 

Hmm... Well, I think I can grab a few pieces of puzzle, but not really a complete one.

 

Anyway, unless AMD release the chipset technical information, there's no telling if any of the reports are accurate.

 

I was just kinda curious how everything connected to each other. Guess you can only see all the chipset details if you are working for motherboard companies. Too bad.

 

Well, thanks anyway.

[Chiyawa]

Okay, this took a while but I managed to piece everything together, and boy, does HWiNFO really report the wrong info. I wonder if some of their testing algorithm needs some fixing?

 

Anyway, here's what I found out how they split the PCIe lanes in Gigabyte X570 Aorus Pro WiFi:

4 lanes go to the PCIe x4 slot,

4 lanes go to M2 slot,

2 lanes go to PCIe x1 slot, each use 1 lane

1 lane go to Ethernet controller,

1 lane go to WiFi,

2 lanes converted to 2 SATA ports,

 

Total usage: 14 lanes. By golly, they disabled 2 PCIe lanes!

 

Well, that's one puzzle solved. Now to figure out the USB controller, how they assigned the ports. So far I know there are 2 USB XHCI controllers managing all USB ports provided by the chipset.

 

According to the pic I posted at the beginning, there are 8 USB 3.2 ports and 4 USB 2.0 ports. I found out that the 4 USB 2.0 ports might have been disabled, as Gigabyte uses USB 2.0 hubs. So...

1 USB-C at back panel

1 USB 3.2 gen 2 at back panel

1 USB-C at motherboard header

4 USB 3.2 Gen 1 headers

2 USB 3.2 Gen 1 converted to 8 USB 2.0 ports, 4 ports at back panel, 4 ports at headers.

1 USB 3.2 Gen 1 used by the Bluetooth.

 

Hmm... They still doesn't add up.