ZEN2 will have Double the L3!

[Mihle]

Someone speculated in that Epyc Rome had a copy of L3 cache for each die on the IO die to get lower latency when a core needs data from another chiplets cache. 1 jump instead of 2.

 

This isn't that right?

[ATFink]

What does 800 MHz IMC mean (Internal memory controller?). How does this affect IPC?

 

How much can we realistically expected the clockspeeds to increase from this 1.4 GHz engineering sample (I assume this is base clock, but who knows really)?

[DeScruff]

6 hours ago, Rauten said:

Holy crap, that CPU has more L3 cache than my 386 had HDD size.

Heheh reminds me when in some interview Richard Garriott (creator of the Ultima series of games) years ago pointed out that Ultima II could completely fit into a "modern CPU's" L2 Cache.

[dizmo]

1 hour ago, vinyldash303 said:

Not to mention @Trixanity pulling the heatsink off sometimes yanks the proc out with it. That's never a good time.

Had that happen the first time I took a Ryzen CPU out. It's just a much worse experience than LGA.

[derr12]

5 hours ago, dizmo said:

I hate PGA chips. Harder to get out of the socket, greater chance of damage when inserting it into the socket.

It's a small gripe, but when one has one and the other doesn't and performance is similar, it's one of the things that will make me sway the other way.

I’ve repasted hundreds of pga chips, never had a problem that was a perminant annoyance. Well except that pentium 90 I dropped.

[CommandMan7]

4 hours ago, Mihle said:

Someone speculated in that Epyc Rome had a copy of L3 cache for each die on the IO die to get lower latency when a core needs data from another chiplets cache. 1 jump instead of 2.

 

This isn't that right?

Yes, I believe it was AdoredTV who predicted that. He's been pretty good at predicting Zen 2 leaks as of so far...

 

 

from 20:38 to 21:26

 

 

[dizmo]

2 hours ago, derr12 said:

I’ve repasted hundreds of pga chips, never had a problem that was a perminant annoyance. Well except that pentium 90 I dropped.

Good job?

[williamcll]

Guess I'll keep saving my money

[CarlBar]

10 hours ago, Techstorm970 said:

That's pretty rad.  Didn't know they had released a 10nm CPU already.  The efficiency boost alone will be huge.  I guess they are still innovating; hell, the increase in efficiency from Kaby Lake to Coffee Lake was pretty impressive given that they both have the 14nm process.

If this is the only reason they're struggling with 10nm, then Imma be SUPER pissed!

 

Having said that, no wonder NVIDIA and AMD are skipping over 10nm with GPUs!  No wonder Intel stole Raja!  10nm must be an engineering nightmare for graphics processing.  Would certainly explain a lot...

 

Intels issue isn;t the performance of their 10nm, it';'s being able to produce usable size dies at usable yield rates that is giving them fits.

 

8 hours ago, Nicnac said:

 

 

My guess would be no. They are increasing the L3 mainly for the extremely large core count cpus because that's where the infinity fabric is running into latency issues. A positive side effect is that higher L3 gives an overall better IPC as well.

This might trickle down to Threadripper where the 32core model (2990WX I believe) is already stressing infinity fabric more than they'd like.

The standard consumer Ryzen might see an upgrade in L3 cache as well but certainly not as big.

Then again, I'm only making assumptions here from what I've read so far but it seems to be the most logical scenario for me. 

 

Whilst i tend to agree we probably won't see so much cache on the desktop, i'd be cautious of assuming that the cache has anything to do with latency. The theoretical physical limit on latency is more than low enough that they could have just made the interconnects low latency enough. And based on AMD's own statements about any single CPU being able to access the full bandwidth of all the memory channels added together they're clearly overcome the data transmission issues that Zen1 and Zen+ clearly had.

 

 

Also for everyone else, anytime you see anything about Zen2 prior to official announcement, it will be based on pre-production silicon. And pre-production silicon allways has issues. AdoredTV has indicated that for Zen 2 the A series silicon is full of issues that is forcing AMD to turn a whole host of things off and downclock everything else quite heavily. This is nothing unusual either, this kind of thing is quite normal. But it does mean what where seeing isn't even the final form. For all we know the L3 caches may have significant sections disabled. I doubt it personally, doublign the cache sounds generous enough but there's no reason they couldn't have doubled it again but had to disable a big chunk of it due to flaws.

[leadeater]

2 hours ago, dizmo said:

Good job?

The good old days of "Twist then lift" has been lost due to LGA. Wasn't a big problem as long as you remembered to break the seal on the paste between the IHS and heatsink, easy enough to forget when you've been dealing with LGA for the last 10+ years.

[leadeater]

7 hours ago, CarlBar said:

i'd be cautious of assuming that the cache has anything to do with latency

It wouldn't unless there is a cache miss, but that's different than more cache reducing cache latency.

 

7 hours ago, CarlBar said:

And based on AMD's own statements about any single CPU being able to access the full bandwidth of all the memory channels added together they're clearly overcome the data transmission issues that Zen1 and Zen+ clearly had.

That's all down to moving all the IMC controllers in to the I/O die instead of each die having a dual channel controller each and having to go through the IF to get non local memory pages. It's actually a very good design move, really obvious once you've seen it but the trick is to actually come up with it .

 

7 hours ago, CarlBar said:

But it does mean what where seeing isn't even the final form

This calls for a good meme 

[Mihle]

28 minutes ago, leadeater said:

It wouldn't unless there is a cache miss, but that's different than more cache reducing cache latency.

 

That's all down to moving all the IMC controllers in to the I/O die instead of each die having a dual channel controller each and having to go through the IF to get non local memory pages. It's actually a very good design move, really obvious once you've seen it but the trick it to actually come up with it .

 

 

Yes, but as there is no connection between the chiplets itself exept to the IO die, it means communication between two chiplets have to do 2 jumps instead of 1. (Unless they do the copy of cache on IO die thing)

[leadeater]

12 minutes ago, Mihle said:

Yes, but as there is no connection between the chiplets itself exept to the IO die, it means communication between two chiplets have to do 2 jumps instead of 1. (Unless they do the copy of cache on IO die thing)

Correct but it does mean every core has equal access to all ram channels and memory pages which is better, well hopefully better more of them time and worse less of the time. Inter thread communication can often be done through system memory anyway so in those cases there isn't an extra hop than would be necessary.

 

Going to be a very interesting review cycle when EPYC 2 comes out.

[Quadriplegic]

6 minutes ago, leadeater said:

Going to be a very interesting review cycle when EPYC 2 comes out.

How many reviewers can even get their hands on something like Epyc?

[leadeater]

2 minutes ago, Quadriplegic said:

How many reviewers can even get their hands on something like Epyc?

ServeTheHome will have multiple different models of them, it's the main area they cover. https://www.servethehome.com/

 

Then Aandtech and Tom's Hardware (pro side) will have the top end SKUs as well. There will be more than that but enough to get information to talk about.

[ZacoAttaco]

1 hour ago, leadeater said:

ServeTheHome will have multiple different models of them, it's the main area they cover. https://www.servethehome.com/

 

Then Aandtech and Tom's Hardware (pro side) will have the top end SKUs as well. There will be more than that but enough to get information to talk about.

We don't talk about Tom's Hardware anymore...

 

/s

[mikat]

15 hours ago, bcredeur97 said:

inb4 having so much cpu cache that you can use it as a type of "ramdisk"

 

 and have speeds north of 1TB per second. because why not.

imagine being able to use GPU memory (HBM 2, 256 GB/s per package ) as a ram disk over the PCIe 4.0 x16 bus

32 GB/s

[mikat]

1 hour ago, leadeater said:

ServeTheHome will have multiple different models of them, it's the main area they cover. https://www.servethehome.com/

 

Then Aandtech and Tom's Hardware (pro side) will have the top end SKUs as well. There will be more than that but enough to get information to talk about.

ServeTheHome do benchmarking for software companies to see how well their software performs, that's why they have so many servers with the latest cpus

source:

Spoiler

Quote

For this exercise, we are using our legacy Linux-Bench scripts which help us see cross-platform “least common denominator” results we have been using for years as well as several results from our updated Linux-Bench2 scripts. At this point, our benchmarking sessions take days to run and we are generating well over a thousand data points. We are also running workloads for software companies that want to see how their software works on the latest hardware. As a result, this is a small sample of the data we are collecting and can share publicly. Our position is always that we are happy to provide some free data but we also have services to let companies run their own workloads in our lab, such as with our DemoEval service. What we do provide is an extremely controlled environment where we know every step is exactly the same and each run is done in a real-world data center, not a test bench.

We are going to show off a few results, and highlight a number of interesting data points in this article.

https://www.servethehome.com/intel-xeon-e-2136-benchmarks-and-review/2/

 

[leadeater]

3 hours ago, ZacoAttaco said:

We don't talk about Tom's Hardware anymore...

 

/s

Who's that? Never heard of them.

 

Spoiler

 

Tom's IT Pro is fortunately a different group of people so they are safe[er] than regular Tom's Hardware 

 

Safe

 

Not safe 

 

 

Edited November 27, 2018 by leadeater

[leadeater]

3 hours ago, mikat said:

ServeTheHome do benchmarking for software companies to see how well their software performs, that's why they have so many servers with the latest cpus

source:

Yep, it's one of my go to places for server hardware stuff. Since they do more than just product review their information is more in depth and/or covers areas of more interest and more applicable to the server industry rather than just runing CB and going "Wow look at those numbers", not they they don't also provide that lol. 

[Doobeedoo]

I wonder how much will latency be improved. Also this will be very good for some workloads. 

[dizmo]

6 hours ago, leadeater said:

The good old days of "Twist then lift" has been lost due to LGA. Wasn't a big problem as long as you remembered to break the seal on the paste between the IHS and heatsink, easy enough to forget when you've been dealing with LGA for the last 10+ years.

The thought of twisting it always freaked me out I just see it as a smarter choice to have the pins in the motherboard. Significantly less chance of them interacting with something.

[leadeater]

2 minutes ago, dizmo said:

The thought of twisting it always freaked me out I just see it as a smarter choice to have the pins in the motherboard. Significantly less chance of them interacting with something.

It's funny because way back then when LGA first became a thing I thought the opposite because CPU weren't that expensive and good motherboard were, now you can get decent motherboard for cheap and CPUs can be extremely expensive. I like the pins to be on the least expensive part 

[CarlBar]

7 hours ago, leadeater said:

It wouldn't unless there is a cache miss, but that's different than more cache reducing cache latency.

 

That's all down to moving all the IMC controllers in to the I/O die instead of each die having a dual channel controller each and having to go through the IF to get non local memory pages. It's actually a very good design move, really obvious once you've seen it but the trick it to actually come up with it .

 

This calls for a good meme 

 

lol.

 

What i meant with the bandwidth thing is that based on the fact that upping the memory clocks, (and this IF clocks), on ryzen had a major positive effect on performance it's obvious the transfer rate of data was a part of Zen1/Zen+ latency issues.Any single CPU being able to access the full memory bandwidth means an IF transfer capacity of over 1.6TB of transfer from the IO die to each core.Thats pretty massive and should completely eliminate any bottlenecking there.

[leadeater]

47 minutes ago, CarlBar said:

Any single CPU being able to access the full memory bandwidth means an IF transfer capacity of over 1.6TB of transfer from the IO die to each core.Thats pretty massive and should completely eliminate any bottlenecking there

I can't find the image but during the presentation I remember them showing the IF linked between the I/O die and chiplets as being 100GB/s which is just exactly enough. 8 channel memory at server RDIMM/LRDIMM spec tops out around that 100GB/s mark, EPYC1 peak best case was 98GB/s when bandwidth testing across the 4 dies stressing each IMC. Each channel on desktops do a bit more than servers because the DDR4 clocks much higher than what servers can use.

 

 

Even on Intel IMCs theoretical maximum is roughly 120GB/s for 8 channels but you're unlikely to actually get it, more like 110 ish.