Intel Offers More Cascade Lake-AP Performance Numbers

[Athan Immortal]

1 minute ago, AluminiumTech said:

On Topic:

I love how Intel is giving up on Hyperthreading in 2018 .

 

Their new Cascade lake AP is 48 Cores and 48 Threads meaning no HT and Epyc 2nd gen will completely destroy it with 64 Cores and 128 Threads.

 

9th gen core i7 has no HT but same core count as i9.

 

Also, 350 watts for 48 Cores and 48 Threads is a bit of a joke (which gets even worse for 700w (2x 350) for 2S Cascade Lake AP)

That new vulnerability that was found and the researchers recommended doing away with SMT and Hyper-threading as they are inherently a security risk. Watch as Intel starts to include it in their slides as a "feature".

[S w a t s o n]

20 minutes ago, GoldenLag said:

There is probably a redit post somewhere whete they compared the Two. They are silly small though.

Snapdragon 845 Rough Estimate:

Spoiler

Zen 2 8 Core Chiplet Estimate:

Spoiler

 

[Taf the Ghost]

30 minutes ago, S w a t s o n said:

I dont think so but maybe, it really depends on how many 7nm chiplets they can make. Turns out the fact that 8 desktop cpu cores are now the size of a phone SoC (less than 80mm square?) yields should be silly good and they can just make wafer upon wafers of these tiny chiplets. If they can make enough 80mm squares and 14nm io chips (these might yield lower than 7nm chiplets) we'll get Ryzen 3rd gen early

Beyond AMD's requirements to produce wafers at GloFo, GloFo's 14nm is one of the best yielding nodes in Semiconductor history. Doesn't seem quite as good as Intel's 22nm (which seems like it was the best ever), but they've been yielding full dies at ~85% for Zen1, which is about 210mm². In fact, the I/O die is almost exactly halfway between Zen1 and Vega for silicon size, so on 14nm it's going to yield extremely well.

 

It's also why I fully expect the Zen3 I/O die to be on 14nm as well. Zen4 and beyond might move over to Samsung or TSMC. Samsung's "8nm" node could be interesting for the I/O die. (Related: we really need a better name for the die. Ripper Die or something like that.)

[RejZoR]

The price and power consumption is going to be astronomical. As things stand right now, Intel can't really touch AMD. And as Linus said, EPYC being backwards compatible, upgrading just CPU's is something companies might consider. With Intel's new socket, it's a no go. AMD's long term investment will pay off, well, long term as well.

[Taf the Ghost]

23 minutes ago, AluminiumTech said:

^^^^

 

Yeah, I hope we do see an 16C/32T R7 3rd gen as well as 12C/24T R7 3rd gen, 8C/16T R5,

 

6C/6T R3 and 4/4 Zen2 based Athlon.

2 Channel DDR4 is not a good mix with 16 cores, outside of gaming. When we get to the DDR5 era, it gets different, so I think the 16c rollout will be limited.

 

What I do think is AMD is probably going to cut that I/O die in 1/4 for roughly 100mm² Controller Die + 2 chiplets. The question is if it's 1 or 2 Zen2 chiplets. I also expect them to attach some 50-100 mm² Vega Chiplet from 14nm. That'll let AMD enter the entire OEM Desktop market. 

[GoldenLag]

37 minutes ago, Athan Immortal said:

That new vulnerability that was found and the researchers recommended doing away with SMT and Hyper-threading as they are inherently a security risk. Watch as Intel starts to include it in their slides as a "feature".

The only issue with that security threath is that it requires turboboost to be off. (Or at least according tl what i know) Something that is very rare on this types of CPUs.

 

Also it is a power saving measure more than anything

[GoldenLag]

19 minutes ago, Taf the Ghost said:

2 Channel DDR4 is not a good mix with 16 cores, outside of gaming

Rome seems to be running 1 channel per die. The only issue is that Consumers really dont need 16 cores. It would be nice and interesting, but not something that everyone wants. 

 

Ive kinda been waiting for Tiny 7nm Vega in mobile CPUs, preferably 7nm offcourse for power efficiency. Idk how Vega 8 compares to intel uhd 620 at idle. 

[RejZoR]

7 minutes ago, GoldenLag said:

Rome seems to be running 1 channel per die. The only issue is that Consumers really dont need 16 cores. It would be nice and interesting, but not something that everyone wants. 

 

Ive kinda been waiting for Tiny 7nm Vega in mobile CPUs, preferably 7nm offcourse for power efficiency. Idk how Vega 8 compares to intel uhd 620 at idle. 

That's not really true anymore. 16 cores (or at least threads) is pretty normal for a bit more demanding casual consumers. Lets say those who buy system now and they expect it to last for several years without any upgrades. If they happen to be gamers or do some heavier load works like encode a video here and there, 16 threads isn't all that exotic anymore thanks to Ryzen. We're talking ~300€ CPU's here (Ryzen 2700X), not 1500€ ones.

 

When I bought my i7 920 it was pretty exotic. 8 threads in times when 4c/4t core was considered high end. Things weren't much different with 5820K. 12 threads when most were running what I used to have half a decade ago on i7 920 (4c/8t).

 

The thing is, core count is scaling high so fast now I'm facing a dilemma where I don't really need to go higher than 16 cores unless software will evolve significantly to justify it. Just like I hit the wall with HDD's at 2TB (and now on SSD), I don't really see the need for top of the line stuff anymore. Which is why my next system will most likely be a mainstream one and not "HEDT" like. Top of th line mainstream will work great.

 

Business use however will benefit greatly from massive amounts of cores as they prefer crunch power over just pure low thread count speed. 16 is a sweet spot that will stay around for quite a while and they really need to bump clocks up to make them interesting for consumers. Intel is already there which is nice (if only they weren't jerking around with garbage thermal interfaces), AMD still needs to get there a bit more seriously.

[Taf the Ghost]

23 minutes ago, GoldenLag said:

Rome seems to be running 1 channel per die. The only issue is that Consumers really dont need 16 cores. It would be nice and interesting, but not something that everyone wants. 

 

Ive kinda been waiting for Tiny 7nm Vega in mobile CPUs, preferably 7nm offcourse for power efficiency. Idk how Vega 8 compares to intel uhd 620 at idle. 

We'll see. There is a nature difference in loads that can scale to 64 cores vs the more Workstation/Individual use cases, which is why I don't think 16c is going to be a very common SKU on desktop. 

 

Doesn't seem to be many rumors about how AMD is going to operate this in the desktop space yet, but my thought is we're getting 2 Chiplets per controller Die on Desktop. Standard SKUs will be 4c through 8c with a Vega chiplet for basic graphics. Then a return of the x800 SKU for 12c & 16c, 2-chiplet without GPU SKUs.

[The Benjamins]

18 minutes ago, RejZoR said:

That's not really true anymore. 16 cores (or at least threads) is pretty normal for a bit more demanding casual consumers. Lets say those who buy system now and they expect it to last for several years without any upgrades. If they happen to be gamers or do some heavier load works like encode a video here and there, 16 threads isn't all that exotic anymore thanks to Ryzen. We're talking ~300€ CPU's here (Ryzen 2700X), not 1500€ ones.

 

When I bought my i7 920 it was pretty exotic. 8 threads in times when 4c/4t core was considered high end. Things weren't much different with 5820K. 12 threads when most were running what I used to have half a decade ago on i7 920 (4c/8t).

 

The thing is, core count is scaling high so fast now I'm facing a dilemma where I don't really need to go higher than 16 cores unless software will evolve significantly to justify it. Just like I hit the wall with HDD's at 2TB (and now on SSD), I don't really see the need for top of the line stuff anymore. Which is why my next system will most likely be a mainstream one and not "HEDT" like. Top of th line mainstream will work great.

 

Business use however will benefit greatly from massive amounts of cores as they prefer crunch power over just pure low thread count speed. 16 is a sweet spot that will stay around for quite a while and they really need to bump clocks up to make them interesting for consumers. Intel is already there which is nice (if only they weren't jerking around with garbage thermal interfaces), AMD still needs to get there a bit more seriously.

Just want to put here.

Competitively AMD does not have to release a 16c mainstream CPU, they could just release a 12c and hold onto the 16c when/if Intel reacts.

 

Its not like intel can just start putting HEDT dies into their mainstream socket.

[Taf the Ghost]

36 minutes ago, GoldenLag said:

Rome seems to be running 1 channel per die. The only issue is that Consumers really dont need 16 cores. It would be nice and interesting, but not something that everyone wants. 

 

Ive kinda been waiting for Tiny 7nm Vega in mobile CPUs, preferably 7nm offcourse for power efficiency. Idk how Vega 8 compares to intel uhd 620 at idle. 

Oh, and the 7nm APUs are late 2019. That's been on the roadmap for a while, as they run a generation behind Server/Desktop.

[S w a t s o n]

On 11/12/2018 at 9:19 AM, The Benjamins said:

Just want to put here.

Competitively AMD does not have to release a 16c mainstream CPU, they could just release a 12c and hold onto the 16c when/if Intel reacts.

 

Its not like intel can just start putting HEDT dies into their mainstream socket.

They wont, they want market share. You know how you suddenly gain market share? Making intel lose the race. They haven't lost the race in a while. 12 Core is winning but 16 core is intel losing. Every enthusiast halo build becomes AMD. Mindshare best share

[The Benjamins]

1 hour ago, S w a t s o n said:

They wont, they want market share. You know how you suddenly gain market share? Making intel lose the race. They haven't lost the race in a while. 12 Core is winning but 16 core is intel losing. Every enthusiast halo build becomes AMD. Mindshare best share

I just figure they can do 12 now, and 16 next year to have a steady improvement year over year.

 

But either way is fine by me.

[CarlBar]

On 11/12/2018 at 11:41 AM, Taf the Ghost said:

The 48 cores with Cascade Lake-AP against the 2x 32c/64t Epyc 7601. The normal use 50% improvement points to that double AVX performance. Charlie at Semi-Accurate has been talking up Rome slaughtering Intel for 2 years. He's not wrong if they normalize AVX performance levels and come with 128c/256t per 2U server.

 

Also Intel chips have to severly downclock when running AVX 512 to not overheat, AMD have confirmed they can maintain base clock in AVX. 

 

On 11/12/2018 at 12:43 PM, GoldenLag said:

The 14nm dies might lead to the Zen 2 Ryzen being quite a bit more expencive than their Zen+ counterpart.

 

Wouldnt be surprising if the top end Zen 2 (if it used 2 7nm dies) being 600$ or so.

 

Interesting to see what config Zen 2 Ryzen will be as fitting am IO die aswell as a 2 7nm dies might be too dense. 

 

There is probably a redit post somewhere whete they compared the Two. They are silly small though.

 

Eh i don;t think they'll be using Rome CPU chiplets at all. AdoredTV went over the binning advantages of chiplet design and manufacturing 2x4 core dies will work much better in that respect for getting 8 chipc onto Desktop CPU's.

 

 Threadripper WX variants will probably use hem, but not Ryzen of threadrippers X variants.

 

On 11/12/2018 at 1:13 PM, Taf the Ghost said:

Beyond AMD's requirements to produce wafers at GloFo, GloFo's 14nm is one of the best yielding nodes in Semiconductor history. Doesn't seem quite as good as Intel's 22nm (which seems like it was the best ever), but they've been yielding full dies at ~85% for Zen1, which is about 210mm². In fact, the I/O die is almost exactly halfway between Zen1 and Vega for silicon size, so on 14nm it's going to yield extremely well.

 

It's also why I fully expect the Zen3 I/O die to be on 14nm as well. Zen4 and beyond might move over to Samsung or TSMC. Samsung's "8nm" node could be interesting for the I/O die. (Related: we really need a better name for the die. Ripper Die or something like that.)

 

I did some reading on process nodes the other day and the IBM 14nm GlFo is using was actually explicitly designed to give usable yields at die sizes upto 700mm².

 

 

 

My personal guesses for 3rd gen Ryzen look something like this, (i plan to do a bigger dedicated thread about the why's and wherefores soonish):

 

IO Die: I expect a uniform IO die across the Ryzen rnage, if they're feeling cheeky they might even unify it with Threadripper. If i was them i'd be looking to build a mem controller that can run dual channel on older chipsets but go quad on newer ones, just for the Ryzen 7 and up, (also again would let them use he same die across Ryzen and Threadripper).

 

Ryzen 5:

 

Option 1; Conservative: 6 cores 12 threads built off 2 4 core dies with the worst core disabled, clocked to the peak the new silicon allows on the same power draw, so about 4.3Ghz base, 5Ghz boost. Safe and will demolish everything but the 9900k in all probability.

 

Option 2; Deathknell: 8 cores 16 threads, 2 4 core chiplets clocked a couple of hundred mhz higher than the Ryzen 7 2700x, so 3.8-3.9Ghz base, 4.4-4.5Ghz boost. Will have similar overall performance to the above but 8c/16t will mean even in highly threaded workloads it's going to eb giving the 9900K price per performance conniptions a 6c/12t model couldn't do.

 

 

Ryzen 7: 

 

Option 1; Conservative: four 4 core dies with the worst core disabled on each. 12c/24t . Clocked upto 4Ghz base, 4.7ghz Boost. This would completely massacre the 9900K on quite a bit less power, (my guesstimate is 115-120 watts, which given how the chiplet architecture spreads the heat out more than a monolith die shouldn't be any harder to cool than the current 105 watt Ryzen 7 2700x).

 

Option 2; All in: 4x4 core chiplets all cores enabled. 16c/32t clocked similarly to the option 2 Ryzen 5. Thermals should be similar to option 1. The 9900K might just barely be able to hold aprity in single threaded with this, but it's ability to compeltly walk away in anything multi-threaded without even trying is going to be a real killer.

 

 

Ryzen 9; Execution Style: AMD doesn't currently have a 9 series Ryzen product and they don't necessarily need to create one, but if they really wanted they could get super cheeky and build their own Zen 2 version of the 9900K, basically take the 16c/32t Ryzen 7 option and crank the clocks upto 4.8Ghz base, 5.1Ghz boost, the max thereticol the Silicon will handle. Again the chiplet layout will make it a bit easier to cool letting AMD get away with a slightly higher peak power draw than even the 9900k, (probably about 175-180 watts). They don;t have to do this, but if they did Intel would basically see it's entire Skylake-X line evaporate under the assault. Intels entire non-Xeon, and most of the Xeon lineup would be benign outmoted by a desktop chip.

 

 

Threadripper 3:

 

X series: Just take the current Ryzen 7 2700x clocks and stick 6 and 8 chiplets respectively onto them for 24c/48t and 32c/64t respectively.

 

WX; As X series but using 6 and 8 lower clocked 8 core Rome CPU Chiplets. You won;t get the PCI-E or Memory bandwidth of rome, but your looking at probably the most hardcore compute chiplet per pound available.Even Cascade Lake is likely to find itself bowing before these things.

 

 

I expect they'll skip Ryzen 9 and go with the option 2 R5 and option 1 R7.

[GoldenLag]

5 minutes ago, CarlBar said:

Eh i don;t think they'll be using Rome CPU chiplets at all. AdoredTV went over the binning advantages of chiplet design and manufacturing 2x4 core dies will work much better in that respect for getting 8 chipc onto Threadrippers WX variants will probably use hem, but not Ryzen of threadrippers X variants.

they dont (after what the public eye and leakers have picked up) have any other chiplets in production when it comes to cores. 

 

they will be using Rome/Zen 2 core chiplets. when it comes to the 14nm IO die however, things are up for speculation as they could keep the current core count with a single 8 core (2x4) chiplet seen in Rome, but they could in theory add a second chiplet. People have also speculated that they might add APU components to the IO die.

 

threadripper will likely see the same IO die as EPYC with a couple of chips physically removed. in one of the interviews they indirectly stated they could remove chiplets at will, and that way allow for lower tier chips. this is unlike Threadripper that needed the dummydies for routing i presume. now sentral IO die with L4 cache will handle that (based on what we know from their presentation. 

 

13 minutes ago, CarlBar said:

Threadripper 3:

 

X series: Just take the current Ryzen 7 2700x clocks and stick 6 and 8 chiplets respectively onto them for 24c/48t and 32c/64t respectively.

 

WX; As X series but using 6 and 8 lower clocked 8 core Rome CPU Chiplets. You won;t get the PCI-E or Memory bandwidth of rome, but your looking at probably the most hardcore compute chiplet per pound available.Even Cascade Lake is likely to find itself bowing before these things.

as stated there is only a single core chiplet we know of and that is 8 (4x2) cores. AMD wants to shove as many chiplets through production and splitting capacity isnt what hey are looking to do when attempting very high volume production.

 

15 minutes ago, CarlBar said:

Ryzen 9

for the love of god. please no, its a dumb naming scheme. i can only see this happen due to AMD having to follow Intel`s naming scheme. and its dumb, very dumb. 

 

[CarlBar]

11 minutes ago, GoldenLag said:

they dont (after what the public eye and leakers have picked up) have any other chiplets in production when it comes to cores. 

 

they will be using Rome/Zen 2 core chiplets. when it comes to the 14nm IO die however, things are up for speculation as they could keep the current core count with a single 8 core (2x4) chiplet seen in Rome, but they could in theory add a second chiplet. People have also speculated that they might add APU components to the IO die.

 

threadripper will likely see the same IO die as EPYC with a couple of chips physically removed. in one of the interviews they indirectly stated they could remove chiplets at will, and that way allow for lower tier chips. this is unlike Threadripper that needed the dummydies for routing i presume. now sentral IO die with L4 cache will handle that (based on what we know from their presentation. 

 

as stated there is only a single core chiplet we know of and that is 8 (4x2) cores. AMD wants to shove as many chiplets through production and splitting capacity isnt what hey are looking to do when attempting very high volume production.

 

for the love of god. please no, its a dumb naming scheme. i can only see this happen due to AMD having to follow Intel`s naming scheme. and its dumb, very dumb. 

 

 

Where not getting Zen 2 for months and months, and months. I'd be stunned if the 4 core was in production yet. They'll get Rome CPU dies sorted before they even start on test production of Ryzen dies as they will doubtless be based on Rome dies, but cut down.

 

Look if AMD does use the Rome die then where going to see desktop 3rd gen ryzen ethier get no clock speed improvement or even a loss in clockspeed compared to Ryzen 2nd gen. Even with Intel being stuck at 14nm thats going to give them at best parity in performance and the 9900k may still have an advantage. And that advantage will last till Zen3 by which tiem Intel will have 10nm.

 

Remember AMD's entire lineup for Zen 2 was built around matching Intel on 10nm. The 9900k isn't the chip they were expecting to go up against. They expected somthing with a good piece bigger performance advantage over the 8700k.

[GoldenLag]

1 minute ago, CarlBar said:

Where not getting Zen 2 for months and months, and months. I'd be stunned if the 4 core was in production yet. They'll get Rome CPU dies sorted before they even start on test production of Ryyzen dies.

except it going to be the same die. they have no reason to use a different die. its only going to make things more expencive, something AMD cannot afford. Supplying chips will be a lot easier by using a single die. the core die is tiny roughly the size of an Snapdragon 845 (i believe its slightly smaller actually based of estimates). also why test produce 2 different dies when you can just use 1. AMD`s entire plan up untill now has been centered around scalability form desktop to server. 

5 minutes ago, CarlBar said:

Look if AMD does use the Rome die then where going to see desktop 3rd gen ryzen either get no clock speed improvement or even a loss in clockspeed compared to Ryzen 2nd gen

um....... what?........  there is a reason why Epyc runs slower than their Ryzen 1 counterpart. there is something called an effiency curve. and for Server the CPUs will be running at close to peak efficiency. on desktop however, they can throw efficiency out the window. Server and Desktop will be using the exact same core die for quite some time, and that wont impact frequency. Server dies dont inherently run slower, they just run where they have best efficiency to performance. clockspeeds are going to increase. 

 

best example is Zen 1 Epyc which uses the exact same dies as Ryzen. under propper cooling these have the exact same overclocking headroom as Ryzen 1 peaking around 4 ghz. (yes Epyc is overclockable). Zen 2 is leaping in max clocks and upped its effiency curve. there wont be any difference between Server and consumer. 

12 minutes ago, CarlBar said:

Remember AMD's entire lineup for Zen 2 was built around matching Intel on 10nm

nonono. it was built with the expectation that 10nm would be out by then. it had nothing to do with matching them. they were going to get Zen 2 as good as possible. And they would then expect that their product would be competing against 10nm icelake when they then launched it.

 

 

AMD will be manufacturing a single die for cores, and likely multiple for IO (these could contain many thing and opens a lot of possibility to their semi-custom section)

[CarlBar]

21 minutes ago, GoldenLag said:

um....... what?........  there is a reason why Epyc runs slower than their Ryzen 1 counterpart. there is something called an effiency curve. and for Server the CPUs will be running at close to peak efficiency. on desktop however, they can throw efficiency out the window. Server and Desktop will be using the exact same core die for quite some time, and that wont impact frequency. Server dies dont inherently run slower, they just run where they have best efficiency to performance. clockspeeds are going to increase. 

 

best example is Zen 1 Epyc which uses the exact same dies as Ryzen. under propper cooling these have the exact same overclocking headroom as Ryzen 1 peaking around 4 ghz. (yes Epyc is overclockable). Zen 2 is leaping in max clocks and upped its effiency curve. there wont be any difference between Server and consumer. 

 

Um you do understand how binnign works? Going from 4 cores per die to 8 hits you hard in the binning department, you just won;t get many chips that can go that high. You can't go from Ryzens 2x4 core dies to 1 x 8 core die and not lose peak clock speed capability in really world terms.

[GoldenLag]

4 minutes ago, CarlBar said:

 

Um you do understand how binnign works? Going from 4 cores per die to 8 hits you hard in the binning department, you just won;t get many chips that can go that high. You can't go from Ryzens 2x4 core dies to 1 x 8 core die and not lose peak clock speed capability in really world terms.

i think you are missing something. Rome and also Zen 2 which is what Ryzen 3 will be using is using 8 cores per die. 

 

binning these chips are going to be relativly easy. Server was allways going to get the best dies regardless of the situation. the situation you are painting is 2 dies being binned seperatly, which isnt great when wanting to minimize waste dies..........

 

also Zen 2 dies are small, like really small. keep in mind they are yielding good Vega 7nm dies at TSMC. their chips will yield well and the consumers have allways had the short end of the stick when it comes to binning. in general chips will hit a certain clockspeed and you design the clockspeeds around that. that way you can have lots of chips running within spec. within that you a variances with the chips. ever heard of silicon lottery? that is just the small difference in chips playing itself out. 

 

Zen 2 is going to have a rough max clockspeed at some frequency regardless of what you do, AMD is simply doing the most with the Chips they get from TSMC. The way they do that is give Serverchips the best chips to improve efficiency, the hedt plattform the slightly worse ones and finally the consumers which will get the short end of the stick. 

 

 

12 minutes ago, CarlBar said:

Ryzens 2x4

note AMD have no 4 core die base design. the closest you get is the APUs that are zeppelin dies cut in half. what they are running is 8 cores on a single die in a 4x2 core setup. see dieshots of Zeppelin dies. 

 

 

 

i didnt think i had to explain this to someone who seemed so invested in AMD leaks over the past few months. 

 

count the chiplets. there are 8, which in each have 8 cores each. making it have 64 cores. 

 

here is threadripper/EPYC with 4 dies each with 2 clusters of 8 cores each. 

 

 

Zen 2 is a continuation of Zen 1. essentially a redesign of a lot of stuff to make it more modular. 

 

you thinking of using smaller 4 core dies might look good on paper, but when taking into consideration how little the consumerside means, they wont design a whole new die for us. they cant, that takes up design teams. something AMD does not have in plenty. from everything we know, it makes no sence for AMD to make a second chip for production, when the one they will be using anyway can be used for everything from mobile laptops to server with no practical downside for them. It simply makes no sence for them to produce a 4 core die at all. 

[CarlBar]

2 minutes ago, GoldenLag said:

i think you are missing something. Rome and also Zen 2 which is what Ryzen 3 will be using is using 8 cores per die. 

 

binning these chips are going to be relativly easy. Server was allways going to get the best dies regardless of the situation. the situation you are painting is 2 dies being binned seperatly, which isnt great when wanting to minimize waste dies..........

 

also Zen 2 dies are small, like really small. keep in mind they are yielding good Vega 7nm dies at TSMC. their chips will yield well and the consumers have allways had the short end of the stick when it comes to binning. in general chips will hit a certain clockspeed and you design the clockspeeds around that. that way you can have lots of chips running within spec. within that you a variances with the chips. ever heard of silicon lottery? that is just the small difference in chips playing itself out. 

 

Zen 2 is going to have a rough max clockspeed at some frequency regardless of what you do, AMD is simply doing the most with the Chips they get from TSMC. The way they do that is give Serverchips the best chips to improve efficiency, the hedt plattform the slightly worse ones and finally the consumers which will get the short end of the stick. 

 

 

note AMD have no 4 core die base design. the closest you get is the APUs that are zeppelin dies cut in half. what they are running is 8 cores on a single die in a 4x2 core setup. see dieshots of Zeppelin dies. 

 

 

 

i didnt think i had to explain this to someone who seemed so invested in AMD leaks over the past few months. 

 

count the chiplets. there are 8, which in each have 8 cores each. making it have 64 cores. 

 

here is threadripper/EPYC with 4 dies each with 2 clusters of 8 cores each. 

 

 

Zen 2 is a continuation of Zen 1. essentially a redesign of a lot of stuff to make it more modular. 

 

you thinking of using smaller 4 core dies might look good on paper, but when taking into consideration how little the consumerside means, they wont design a whole new die for us. they cant, that takes up design teams. something AMD does not have in plenty. from everything we know, it makes no sence for AMD to make a second chip for production, when the one they will be using anyway can be used for everything from mobile laptops to server with no practical downside for them. It simply makes no sense for them to produce a 4 core die at all. 

 

Actually i've just started getting back into computers in a big way this last month and spent most of last week catching up on the AMD stuff. My understanding was that Ryzen is a dual die design, (there's even an apparent split between them in pictures of them delidded).But a bit of digging in response shows that actually yes it;s a single odd looking die.

 

In that case it may make sense, (but they're still going to have to do at least 1, possibly 2 new IO dies, don't think for a minute thats going to be magically cheaper than designing a new CPU die). But if they do go that route they're basically going to have to make Ryzen 5 8 core otherwise they're wasting a ton of silicon. 

 

Though what makes you think server would get the best binned chips when the exact reverse happened for Epyc 1 i don't know.

[GoldenLag]

4 minutes ago, CarlBar said:

Though what makes you think server would get the best binned chips when the exact reverse happened for Epyc 1 i don't know.

last time i checked Threadripper got the top 5 % dies. Epyc pretty much got the top and Ryzen got everything else.

 

its standards prosedure for server to get the best dies to get the best possible effiency. 

 

5 minutes ago, CarlBar said:

But if they do go that route they're basically going to have to make Ryzen 5 8 core otherwise they're wasting a ton of silicon. 

not neccesarly depending on what design they go for. as far as i know, unlike Zen 1 which required all dies to be present on a substrate for it to work, due to the l4 cache on the IO die they do not need every chip "slot" to be filled. they could essentially have Ryzen 3 chips with 1 7nm die and Ryzen 7 with 2 7nm dies. 

[Taf the Ghost]

As a note from people attempting to work out the design for Rome after it went from Rumor to Leak of the +1 design, the general view is that it's an 8 core CCX now rather than 2x 4 core CCX per chiplet. It's very possible AMD can do something like 6c, 8c, 10c, 12c and 16c parts on AM4. I still personally expect the Ryzen 3200 through 3700 will be 1 Chiplet + 1 Polaris/Vega chiplet to hit the entire normal OEM market, but AMD has avoided mentioning the CCX layout for Rome so far.

 

Just something to keep in mind.

[CarlBar]

4 minutes ago, GoldenLag said:

last time i checked Threadripper got the top 5 % dies. Epyc pretty much got the top and Ryzen got everything else.

 

its standards prosedure for server to get the best dies to get the best possible effiency. 

 

Nope Ryzen has the higher clocks than both. Thats what binning is. A 4 core chiplet would let them eek out a lot more frequency though than an 8 core.

 

5 minutes ago, GoldenLag said:

not necessary depending on what design they go for. as far as i know, unlike Zen 1 which required all dies to be present on a substrate for it to work, due to the l4 cache on the IO die they do not need every chip "slot" to be filled. they could essentially have Ryzen 3 chips with 1 7nm die and Ryzen 7 with 2 7nm dies. 

 

We have no confirmation of an L4 cache AFAIK. We also don't know the internal layout of the chiplets. They could have designed them that way but it's the silicon itself that costs the most so not putting the transistors in during process may not save them much, (or am i not getting what your saying right).

[CarlBar]

2 minutes ago, Taf the Ghost said:

As a note from people attempting to work out the design for Rome after it went from Rumor to Leak of the +1 design, the general view is that it's an 8 core CCX now rather than 2x 4 core CCX per chiplet. It's very possible AMD can do something like 6c, 8c, 10c, 12c and 16c parts on AM4. I still personally expect the Ryzen 3200 through 3700 will be 1 Chiplet + 1 Polaris/Vega chiplet to hit the entire normal OEM market, but AMD has avoided mentioning the CCX layout for Rome so far.

 

Just something to keep in mind.

 

This too, though the idea they'll limit Ryzen to 1 chiplet strikes me as unlikely. It just dosen;t fit how AMD's been going with the core/thread count.

[GoldenLag]

8 minutes ago, CarlBar said:

Nope Ryzen has the higher clocks than both. Thats what binning is. A 4 core chiplet would let them eek out a lot more frequency though than an 8 core.

except binning isnt all about core clocks. also Ryzen didnt overclock better than threadripper. and as far as i know, Epyc didnt overclock any worse than neither. if they were making 4 core chiplets, they would be cutting down an allready small die, they would probably run into solder issues. 

10 minutes ago, CarlBar said:

We have no confirmation of an L4 cache AFAIK. We also don't know the internal layout of the chiplets. They could have designed them that way but it's the silicon itself that costs the most so not putting the transistors in during process may not save them much, (or am i not getting what your saying right).

doublechecked, i might have mixed some slides up, but at least the general consensis is some form of l4 cache as it is the only way that we can make sence of it. the infinity fabric now communicates through the IO die. which in turn dictates some sort of cache should be in place, though we dont know entirely