Intel Knights Mill, Stratix 10 + future of cpu making, and Scorpio

[NumLock21]

Ian Cutress from Anandtech, was at the Hot Chips event and did a few live blogs on the upcoming Intel cpus and Xbox One X Scorpio Engine

 

Microsoft Xbox One X Scorpio Engine

Spoiler

 

 

 

Intel Knights Mill

Quote

 

• Machine Learning' is a wide umbrella
• We need to put in the smarts to the algorithms
• Neural Networks are not new - we learned about them in the 60s
• The blessing and the cure is the curated data and self-training
• A lot of focus on image recognition
• We have solutions, from Xeon to Xeon Phy, to FPGA, to Deep Learning in the Crest Family
• Announcing Knights Mill, building on top of Knights Landing
• 4x Deep Learning perf over Knights Landing
• We want the cake and eat it too: so we have embedded memory and DDR4
• 16GB of MCDRAM
• 2-way OoO, 4-way SMT, AVX-512 with VNNI, new Quad FMA
• TLP, ILP, DLP and PLP
• Based on KNL, up to 6-channel of DDR4, 36 lanes PCIe
• Same core config of KNL: 2 cores sharing 1MB of L2, one VPU per core
• Using the Mesh interconnect
• Number of cores withheld for today (although that slide says 36 tiles)
• To be launched in Q4

 

 

Spoiler

 

 

 

 

 

 

Intel Stratix 10 + future of processor manufacturing

Quote

 

• As we move to smaller process nodes, it makes massive monolithic chips harder to create. Yields go down and it gets expensive
• The solution to this is to create a multi-die package, using interconnects between the chips. We've seen this for years, and most recently in Xeon Phi and EPYC
• Die to die communication now becomes an area calling out for innocation
• Although the future of the technology can mean that we will have multiple dies on package made at different process nodes. The cores at one node, the onboard memory at another node, perhaps integrated accelerators/RF at other nodes etc
• This is why the technology comes across as fascinating to the future of Intel's processor lines. Especially as we hit 10nm and below
• Intel's latest 14nm FPGA solution
• Stratix 10 implementing HBM using Intel's latest EMIB (embedded multi-die interconnect bridge) technology
• Intel Stratix 10 with four tranceiver chiplets and two DRAM chiplets
• EMIB is a mid-way point in this. Signals still go through the package, but the package is modified to allow for shorter paths and faster connectivity
• We'll see it in FPGAs first, that require access to high bandwidth memory (and customers are willing to pay)
• Using multibump pitch on the FPGA die
• Interposer is also available, but EMIB is only localised digital connections. Other IOs/RG are unaffected, and can use multiple bridges. In an interposer, you need to have TSVs for non-cross chip communication. All the signals need to go through
• So reduced fabrication and assembly, cost effective, high perf solution. Also no reticle size limits now: build a system as large as your package.
• EMIB is a simple parallel IO circuitry for lower power and lower latency and larger scalability
• AIB a small sliver for communication and data streaming at 1 Tbps
• AIB on chiplet and AIB on FPGA. Now it becomes a Lego system. Stick what you need together when the AIB is standard
• Chiplets can be large or small as whatever is needed. Chiplets can have multiple AIBs to connect to other silicon.
• Create dies with AIB and UIB ports, then play lego to create a family of products
• Modular platform enables cost-effective upgrades. No need to respin a die, just replace chiplets with other IP blocks

 

Spoiler

 

 

 

http://www.anandtech.com/show/11740/hot-chips-microsoft-xbox-one-x-scorpio-engine-live-blog-930am-pt-430pm-utc

http://www.anandtech.com/show/11741/hot-chips-intel-knights-mill-live-blog-445pm-pt-1145pm-utc

http://www.anandtech.com/show/11748/hot-chips-intel-emib-and-14nm-stratix-10-fpga-live-blog-845am-pt-345pm-utc

[Jito463]

2 minutes ago, NumLock21 said:

• As we move to smaller process nodes, it makes massive monolithic chips harder to create. Yields go down and it gets expensive
• The solution to this is to create a multi-die package, using interconnects between the chips. We've seen this for years, and most recently in Xeon Phi and EPYC
• Die to die communication now becomes an area calling out for innocation (sic)
• Although the future of the technology can mean that we will have multiple dies on package made at different process nodes. The cores at one node, the onboard memory at another node, perhaps integrated accelerators/RF at other nodes etc
• This is why the technology comes across as fascinating to the future of Intel's processor lines. Especially as we hit 10nm and below

Congratulations on joining the party, Intel.

 

[Coaxialgamer]

Looks to me like Ms basically crammed an r9 290x (on 14nm ) in their SoC

[PCGuy_5960]

9 minutes ago, NumLock21 said:

So will Intel say that their CPUs are "glued together"? 

[NumLock21]

Quote

• So reduced fabrication and assembly, cost effective, high perf solution. Also no reticle size limits now: build a system as large as your package.

 

[PlayStation 2]

will they be using glue to connect multiple chips into one

[Taf the Ghost]

Chiplet is almost here. Though some of the rumors is the first consumer product with the approach will be Navi in 2019. We'll see. This tech has actually been "where it's going" for a while, it just wasn't quite worth the investment when node shrinks happened so quickly.

[Taf the Ghost]

Just now, Dan Castellaneta said:

will they be using glue to connect multiple chips into one

EIMB really is gluing dies together. 

[The Benjamins]

3 minutes ago, NumLock21 said:

 

hmm it kinda like what AMD Glued™ CPU's brought to the market. :^)

[NumLock21]

9 minutes ago, PCGuy_5960 said:

So will Intel say that their CPUs are "glued together"? 

They'll probably come up with a scientific or medical name for that. Something that's really long and really difficult to pronounce.

[captain cactus]

39 minutes ago, PCGuy_5960 said:

So will Intel say that their CPUs are "glued together"? 

Sort of. Intel is going the Vega way with multiple nodes on a single package (Vega is 14nm core with some node for HBM on a 40nm interposer). So yes, still glued together, but with the logic (like IO) that doesn't require a lot of complex paths on a cheaper to produce bigger node and then putting that together to form one CPU.

[Jito463]

46 minutes ago, NumLock21 said:

So reduced fabrication and assembly, cost effective, high perf solution. Also no reticle size limits now: build a system as large as your package.

[8uhbbhu8]

Hmmm Intel... I see you are taking a page out of AMDs book! 

[SansVarnic]

49 minutes ago, NumLock21 said:

They'll probably come up with a scientific or medical name for that. Something that's really long and really difficult to pronounce.

mucilage [myoo-suh-lij]

[Sauron]

 

this just looks a lot like Jaguar again... although it is to be expected if they want retrocompatibility.

[NumLock21]

46 minutes ago, Sauron said:

 

this just looks a lot like Jaguar again... although it is to be expected if they want retrocompatibility.

 

[AnonymousGuy]

1 hour ago, Jito463 said:

So I can build an average and disappointing system....

 

[MyName13]

So Intel will glue different dies to make one cpu (like epyc and TR) unlike AMD who puts both ccx modules on the same die?This makes far more sense than ryzen, what's the point of ccx modules if they're on the same die?Where's scalability in that if high end needs to outsell the low end to create more defective dies?

[Trixanity]

Anyone knows how EMIB stacks up and compares to what AMD has in the pipeline? It seems somewhat different to me than Infinity Fabric yet seems to do pretty much the same thing.

[Sniperfox47]

13 hours ago, Jito463 said:

Congratulations on joining the party, Intel.

 

Except Intel was using interposers first, long before AMD... on Xeon Phi...

[Misanthrope]

13 hours ago, Coaxialgamer said:

Looks to me like Ms basically crammed an r9 290x (on 14nm ) in their SoC

If the heat output doesn't ends up creating a singularity that's actually quite the feat.

[Agosto]

13 hours ago, Coaxialgamer said:

Looks to me like Ms basically crammed an r9 290x (on 14nm ) in their SoC

It's actually a custom version of Polaris

[MyName13]

Isn't it a little worrying that next gen consoles with hexa or octa core ryzen and vega GPU will come out in 2-3 years which will make ps4 pro and xbox one x useless?These "premium 4k" consoles will have unbelievably short lifespan when compared to ps3/xbox 360 and ps4/xbox one, so what's the point of these consoles?

[leadeater]

52 minutes ago, Sniperfox47 said:

Except Intel was using interposers first, long before AMD... on Xeon Phi...

Clovertown and Core 2 Quad too 

 

That's 2006 btw.

[The Benjamins]

14 hours ago, Sauron said:

 

this just looks a lot like Jaguar again... although it is to be expected if they want retrocompatibility.

We knew it was Jaguar cores, if they wanted zen it would be delayed by at least a year.