Performing word-addressability on byte addressable SRAM.

[Coaxialgamer]

I'm working on a project, but I'm having issue with something that i had previously overlooked. 

I have a computer with a 4 byte word size, and i want to store values in an sram module, in big endian format. 

Problem is, SRAM chips only support byte-addressing as far as i know (only one byte can be accessed and written/read from at any given step) 

The particular chip i am looking at is this

http://www.mouser.com/Search/m_ProductDetail.aspx?Alliance-Memory%2fAS6C4008-55PCN%2f&qs=sGAEpiMZZMt9mBA6nIyysPeGHDtAZQ%2bHv1ODopTep98%3d

 

I need a through-hole design, and i also need a reasonable capacity (over 1mbit), while using a parallel interface( not serial SRAM) 

 

I've come up with several potential solutions, but they all have unacceptable drawbacks. 

- run the ram clock at 4x the speed of the  rest of the circuit, and perform additions on the address 3 times. Problem is i would need a full adder for those calculations on the memory address, which would be too expensive, not to mention the latency of the SRAM chips would require stalling the pipeline on the processor, which would cripple performance (over 200ns latency, worse than DRAM) 

- I could use 4 banks of SRAM, with information cloned on all banks. That would be expensive, and i would still need an adder for address calculations. 

 

Any easy way to do this? 

 

[SEGFAULT]

You might be on the wrong forums for this,

try EEVBLOG.

 

But while your here:

Instead of trying to stuff 32 bits into a 8 bit datapath why not just use 4 of the ram chip in parallel each handling one byte of the word. Syncronise the address fed to all of them and they become one simulated 512x32 bit SRAM.

What processor are you using out of curiosity.

[Coaxialgamer]

2 hours ago, SEGFAULT said:

You might be on the wrong forums for this,

try EEVBLOG.

 

But while your here:

Instead of trying to stuff 32 bits into a 8 bit datapath why not just use 4 of the ram chip in parallel each handling one byte of the word. Syncronise the address fed to all of them and they become one simulated 512x32 bit SRAM.

What processor are you using out of curiosity.

I'm building my own processor ( design and prototyping atm)   which is why i need to figure this stuff out. I thought of that tbh, but i wasn't sure about some technicalities. From the beginning, I've always felt that a 32 bit word should contain 4 individually addressable bytes, with each word on an address being a multiple of 4. 

I was under the impression that linking 4 memory chips under a single address would effectively be the same as having 32 bit bytes.

After speaking to some people on quora about it, it seems this is less important than I  initially thought, and I will just add an instruction that allows the process to read/write  8 bits in a word, given a word and an offset. 

[SEGFAULT]

What you said above is correct. If you are designing an instruction set from scratch note that 32 bits is a very large word to work with, maybe first consider how big you want your addressable memory area to be without paging, and how many instructions you need, from there you can make a more technical decision on word length.

 

when it comes to system design I would also recommend hacking together a simulation of your design in software (coding a CPU in nearly any language is relatively easy (LUA is a good choice though)) and testing it with some mock programs before turning on your soldering iron.

 

Also worth mentioning is that systems that use multi word instructions in my experience (yes I am also crazy enough to design my own instruction set) are easier to design, as if you use full word addresses (AKA your addresses are the same length as your word) everything lines up in an intuitive way. of course I am working with an 8 - 10 bit word and multi word instructions allowed me to leverage all 256 bytes of available address space which was sort of a must. 

[Coaxialgamer]

48 minutes ago, SEGFAULT said:

What you said above is correct. If you are designing an instruction set from scratch note that 32 bits is a very large word to work with, maybe first consider how big you want your addressable memory area to be without paging, and how many instructions you need, from there you can make a more technical decision on word length.

 

when it comes to system design I would also recommend hacking together a simulation of your design in software (coding a CPU in nearly any language is relatively easy (LUA is a good choice though)) and testing it with some mock programs before turning on your soldering iron.

 

Also worth mentioning is that systems that use multi word instructions in my experience (yes I am also crazy enough to design my own instruction set) are easier to design, as if you use full word addresses (AKA your addresses are the same length as your word) everything lines up in an intuitive way. of course I am working with an 8 - 10 bit word and multi word instructions allowed me to leverage all 256 bytes of available address space which was sort of a must. 

Well, one of the set ideas I've had for this project was to build a risc-type arch, with a fixed instruction length, and would only perform register-register operations, with load/store for interfacing with ram. 

I don't want to have to deal with the insane memory limitations of older systems, so out of the box i was set for a 24bit addressing scheme, which would be sufficient for memory and I/O. 

I'm borrowing a few designs philosophies from MIPS for design convenience. 

 

I'm not quite sure how i would go about implementing a multi word arch, and i am a bit concerned that it would be too expensive in terms of cycles ( fetching 2 16bit words would be 2 steps/cycles correct?) 

 

I'll be designing it on an FPGA first, so i can easily perform modifications while writing the assembler.