Intel Introduces New Mesh Architecture For Xeon And Skylake-X Processors

[VagabondWraith]

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Intel's Akhilesh Kumar, the Skylake-SP CPU architect, penned a blog post today announcing the company's new on-chip mesh architecture for its Xeon Scalable Processor platform.
Intel's Scalable Processor platform is the company's re-branding of its venerable Xeon processor lineup, and due to the company's continued use of optimized server processor die for its HEDT (High-End Desktop) lineup for enthusiasts and workstations, the new architecture has wormed its way into the forthcoming Skylake-X family.
Intel's new mesh topology goes head-to-head with AMD's Infinity Fabric, which resides in its Ryzen, ThreadRipper, and EPYC processors.

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Intel's new mesh architecture made its debut on the company's Knights Landing products, but the move to the more mainstream server SKUs and high-end desktop models is designed to bring about new levels of interconnect efficiency for those markets. Aside from the interconnect, a few key attributes pop out. Intel has moved the DDR4 controllers to the left and the right sides of the die--similar to the Knights Landing design--whereas the company has typically positioned them at the bottom for ring bus designs. We'll examine that shortly.

Intel aligned its new mesh topology into a grid of rows and columns that connect the cores and caches, along with the memory and I/O controllers. Notably, there are no buffered switches between disparate rings--it's simply a large mesh, so it eliminates one of the major traffic checkpoints for high core count dies entirely. The switch connections at each intersection of the grid allow for more direct communication between the components, thus providing faster pathways through intelligent scheduling. There also appears to be a circular design to the intersections, which likely allows for more optimized data path scheduling.
The ability to 'stair-step' data through the cores allows for much more complex, but efficient, routing among the elements. Intel also indicates that the new ring has increased bandwidth, which helps speed data traffic among the cores and the caches that feed them. The mesh is also responsible for traffic to and from main memory, so it has an impact on RAM throughput and latency as well.
Data also flows in from the PCIe controllers at the top of the die, along with the two inter-socket links. The inter-socket links manage data flow between processors in 2+ socket server configurations. In the past, Intel has employed its QPI (QuickPath Interconnect) for cross-socket communication, but it's rumored to employ a new UPI interconnect for Skylake server CPUs (Purley). Intel hasn't specified the exact frequency of the new mesh, but has indicated that it has a lower frequency and voltage than the ring bus design, though it still delivers high bandwidth and low latency. That alone is an important achievement.
The modular and distributed design should allow Intel to add more cores to its die without imposing crushing performance and power consumption penalties. The mesh design also reduces latency variability when requesting data from far-flung LLC banks, which allows software to treat it as one large unified last-level cache.

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As Intel indicates in its blog on the mesh announcements, this generic diagram “shows a representation of the mesh architecture where cores, on-chip cache banks, memory controllers, and I/O controllers are organized in rows and columns, with wires and switches connecting them at each intersection to allow for turns. By providing a more direct path than the prior ring architectures and many more pathways to eliminate bottlenecks, the mesh can operate at a lower frequency and voltage and can still deliver very high bandwidth and low latency. This results in improved performance and greater energy efficiency similar to a well-designed highway system that lets traffic flow at the optimal speed without congestion.”

 

So... this looks like something that AMD is using in their "Infinity Fabric." Since Nehalem, Intel has used a "ring-bus" design, but over several generations, it has become quite large and was time for a more efficient implementation.

 

The image above is a simplified version of the new "mesh" technology. In the link below, you can find the ring-bus diagrams and see how unfeasible it has become. The interesting part will be comparing AMD "Infinity Fabric" vs Intel "Mesh" implementations. Nice to see new tech coming to life!

 

https://www.pcper.com/news/Processors/Intel-Skylake-X-and-Skylake-SP-Utilize-Mesh-Architecture-Inter-Chip-Communication

[ARikozuM]

I can't wait until AMD releases Vinyl CPUsuit and Intel's next-gen Dakimakura! 

 

For those of you who don't know what a dakimakura is:

Spoiler

 

For those who know what I'm talking about: Did you really think I was going to put a cute girl? Well, I was going to, but this was funny as the [second] result for dakimakura.

 

[goodtofufriday]

TLDR: Intel is only announcing things after AMD news come out so that we dont forget them. 

[Dash Lambda]

I wonder how much of this is stuff they had hidden in their hat just in case and how much is them frantically rifling through their pockets for paperclips and bits of string.

[leadeater]

Would have liked to see the 28/32 core diagram, looks like they are using 8 core groupings but way too hard to tell on a 14 core die.

[CommandMan7]

Due to the fact this is being adapted from Knights landing rather than being designed specifically for HEDT, I'm highly doubtful it will provide efficiency and scaling for consumers to the extent that Infinity Fabric does.

[Dylanc1500]

Hasn't this been known since around 2015 when they talked about Purley the first time?

 

In fact, it was June of 2015 when they announced UPI "Purley" saying it would be part of the "upcoming" Skylake architecture. They even knew there was going to be 28 core SKU.

 

I feel like I'm the only one remembering all of this.

[79wjd]

1 hour ago, Dash Lambda said:

..... and how much is them frantically rifling through their pockets for paperclips and bits of string.

You can do anything with various lengths of wire. 

 

[Taf the Ghost]

2 minutes ago, goodtofufriday said:

TLDR: Intel is only announcing things after AMD news come out so that we dont forget them. 

You're right, Intel really is doing the "see, look at us!" thing.  That's not a good place to be as a Market Leader.

[ARikozuM]

5 minutes ago, Taf the Ghost said:

You're right, Intel really is doing the "see, look at us!" thing.  That's not a good place to be as a Market Leader.

Reminds me of jocks flexing their muscles in chem class.  "You get an A! For not breaking the beaker while stirring!"

[AnonymousGuy]

2 hours ago, Dylanc1500 said:

Hasn't this been known since around 2015 when they talked about Purley the first time?

 

In fact, it was June of 2015 when they announced UPI "Purley" saying it would be part of the "upcoming" Skylake architecture. They even knew there was going to be 28 core SKU.

 

I feel like I'm the only one remembering all of this.

Yeah but people are just being dumb and act like CPUs are designed and fabbed in 4 weeks.  

 

Hell I think Skylake's design started in 2013 or some shit.

[Dylanc1500]

6 minutes ago, AnonymousGuy said:

Yeah but people are just being dumb and act like CPUs are designed and fabbed in 4 weeks.  

 

Hell I think Skylake's design started in 2013 or some shit.

It was definately in developement at that time due to being in some of their roadmaps back in 2013.

[Dash Lambda]

9 hours ago, Dylanc1500 said:

Hasn't this been known since around 2015 when they talked about Purley the first time?

 

In fact, it was June of 2015 when they announced UPI "Purley" saying it would be part of the "upcoming" Skylake architecture. They even knew there was going to be 28 core SKU.

 

I feel like I'm the only one remembering all of this.

It's moreso the timing of them actually deciding to use it. If it goes back that far, then I'd say this is something they hid in their hat, rather than random stuff they just managed to pull out of their pockets like the 4 core and 14-18 core X299 parts.

[NumLock21]

10 hours ago, djdwosk97 said:

You can do anything with various lengths of wire. 

 

Can make anything with strings when you got the right tool

 

[tom_w141]

1 hour ago, Dash Lambda said:

It's moreso the timing of them actually deciding to use it. If it goes back that far, then I'd say this is something they hid in their hat, rather than random stuff they just managed to pull out of their pockets like the 4 core and 14-18 core X299 parts.

Agreed they are just holding back anything they develop because there is no need to push forward and innovate. Oh competition? *opens filing cabinet of almost ready concepts and plucks a few out* there we go, done. It's just further proof of their deliberate market stagnation

[Dylanc1500]

22 minutes ago, tom_w141 said:

Agreed they are just holding back anything they develop because there is no need to push forward and innovate. Oh competition? *opens filing cabinet of almost ready concepts and plucks a few out* there we go, done. It's just further proof of their deliberate market stagnation

Depending on what view point you take it could be a slightly good thing. With that being the case they have been able pump a ton of extra capital into R&D and develope some awesome things. They just aren't releasing all their cards at once as that could be more detrimental as a business. I'm just trying provide some perspective from their angle of the game.

 

8 minutes ago, CUDA_Cores said:

Intel "mesh architecture" = Infinity fabric

Sort of, they are somewhat accomplishing one of the same feats in two entirely different ways.

Not to mention like you said above, they have had this in their cards since at least 2013.

[tom_w141]

19 minutes ago, Dylanc1500 said:

Depending on what view point you take it could be a slightly good thing. With that being the case they have been able pump a ton of extra capital into R&D and develope some awesome things. They just aren't releasing all their cards at once as that could be more detrimental as a business. I'm just trying provide some perspective from their angle of the game.

Their angle is doing less work is better for business. R&D costs $$$, if you don't need to spend those $$$ then profits are higher. This is why the year on year gains have been so low recently.

[Dylanc1500]

2 hours ago, tom_w141 said:

Their angle is doing less work is better for business. R&D costs $$$, if you don't need to spend those $$$ then profits are higher. This is why the year on year gains have been so low recently.

Their low gains on "performance" from architechure to architechure isn't the only thing they R&D. They are trying to push different things. A great example for them is AVX 512F they are great with it, as it is highly efficient and pushes the hardware. They also have spent a lot developing things like Optane as well.

 

My point is unless someone gets a in-depth breakdown of Intel's spending, no one should be making assumptions on them sitting back doing nothing. They have a Rolodex of stuff in line, that way they don't end up with a 5 plus year stagnation. That's just a smart buisness move in case someone comes along to compete.

[PCGuy_5960]

15 hours ago, VagabondWraith said:

So... this looks like something that AMD is using in their "Infinity Fabric."

Intel should name their design "Infinite Fabric"

[VagabondWraith]

18 minutes ago, PCGuy_5960 said:

Intel should name their design "Infinite Fabric"

Inferior Fabric.  

[PCGuy_5960]

Just now, VagabondWraith said:

Inferior Fabric.  

Huh. I thought you were an Intel Fanboy

[TacoSenpai]

Its a race to see who will claim the infinity stones first.  We saw what that shit did to Jarvis!

[VagabondWraith]

15 minutes ago, PCGuy_5960 said:

Huh. I thought you were an Intel Fanboy

Nah, I was talking AMD POV  

[NumLock21]

I wonder if this mesh architecture is their Omni-Path fabric found on Xeon Phi or something totally new.

[Dylanc1500]

56 minutes ago, NumLock21 said:

I wonder if this mesh architecture is their Omni-Path fabric found on Xeon Phi or something totally new.

This is the exact same thing it is just a different name. There is a reason they use the same socket. Knights landing and Skylake are both using 100G OPI.