PCIe 4.0 *FINALLY* Finalized

[knightslugger]

Just now, tlink said:

now make it rgb for extra data throughput and cool light effects.

if you see FO traces, ur doing it wrong.

[Sniperfox47]

1 minute ago, tlink said:

now make it rgb for extra data throughput and cool light effects.

lol if you have optical traces and can see the lights moving through them, either your eyes are magic or I think you're doing something wrong xP

[tlink]

5 minutes ago, Sniperfox47 said:

lol if you have optical traces and can see the lights moving through them, either your eyes are magic or I think you're doing something wrong xP

 

6 minutes ago, knightslugger said:

if you see FO traces, ur doing it wrong.

rgb magic is real my dudes

[Prysin]

5 hours ago, Sniperfox47 said:

Not sure how we got a post about the 5.0 announcement but somehow missed that the 4.0 spec is finalized after sitting in limbo for a long time.

 

http://techreport.com/news/32064/pcie-4-0-specification-finally-out-with-16-gt-s-on-tap

 

 

While full details aren't yet available for the final spec, the details we do have so far are pretty juicy. Huge sweeping changes to the PHY layer should lead to better latency and much lower power use, so there's the possibility we could start to see this in high end ARM devices.

 

With 5.0 being officially announced at the same time, with a planned release in just two years it'll be interesting to see if AMD or Intel even bother to impliment this on the consumer side of things.

 

 

 

 

Products with it are on their way but keep in mind a lot of these are likely Enterprise products for high end servers where existing PCIe 3.0 interconnects are being fully loaded. I'd be really shocked if there's anything on the consumer side coming Immediately.

 

If only they had announced that dark text on dark theme is a terrible idea. 

[Sakkura]

3 hours ago, Terodius said:

Actually high-end SSDs are already close to hitting a wall with 3.5+GB/s sequential speeds. The 4x PCIe interface has a theoretical 4GB/s limit although in practice it's slightly less due to encoding overhead. Probably by this time next year we'll have an SSD that can saturate it.

The encoding overhead of PCIe 3.0 is minimal. An x4 link has a usable throughput of 3.94 GB/s. 

[Doobeedoo]

Nice as far as lanes and more further support. More stuff can be added and using less. GPUs and SSDs hold well now on current one.

[Juanitology]

44 minutes ago, Sakkura said:

The encoding overhead of PCIe 3.0 is minimal. An x4 link has a usable throughput of 3.94 GB/s. 

That's why I said "slightly" less. It's like a 1.5% overhead so I think my wording was appropriate. Try to read a comment before writing a dumb answer that merely adds noise and doesn't contribute to the conversation.

 

My point still stands regardless. Consumer nvme drives have been adding around 500MB/s sequential speed every year since they launched in 2014 with a baseline of almost 2GB/s. We're now at 3.5GB/s sequential read for Samsung's 960 Pro, and the 950 Pro was at 2.5GB/s, so it doesn't seem unreasonable that they'll have a 4+GB/s capable model for the next iteration which is due in Q3 or Q4. 

[Sakkura]

The 960 Pro doesn't really hit 3.5GB/s. More like 2.7-2.8. And that's only in reads.

 

Also, consumer SSDs in general are probably going to stagnate or become a little slower, not faster.

[Kamina]

Video cards that fully saturate PCIe 4.0, when?

[Drak3]

4 hours ago, Terodius said:

Consumer nvme drives have been adding around 500MB/s sequential speed every year since they launched in 2014 with a baseline of almost 2GB/s. We're now at 3.5GB/s sequential read for Samsung's 960 Pro, and the 950 Pro was at 2.5GB/s, so it doesn't seem unreasonable that they'll have a 4+GB/s capable model for the next iteration which is due in Q3 or Q4.

At high que depths. Consumer workloads rarely manage this, and most that do are benchmarks. Realisitcally, SATA III speeds aren't bottlenecking our tasks.

 

3 hours ago, Sakkura said:

The 960 Pro doesn't really hit 3.5GB/s. More like 2.7-2.8. And that's only in reads.

 

Also, consumer SSDs in general are probably going to stagnate or become a little slower, not faster.

Because Sakkura didn't quote you, I'll quote 'em so that you're more likely to see it.

[ARikozuM]

3 minutes ago, Kamina said:

Video cards that fully saturate PCIe 4.0, when?

When AMD stops releasing refreshes...

 

When Intel releases another dGPU.

[Sniperfox47]

6 hours ago, Drak3 said:

Realisitcally, SATA III speeds aren't bottlenecking our tasks.

Realistically they totally are. Not because of throughput but because of latency. NVMe is orders of magnitude lower latency than AHCI

 

Same reason Optane is going to be great once they work out write optimizations for it. The latency is waaaaaaaaaaaaay lower than a traditional flash SSD.

[Prysin]

20 hours ago, Sniperfox47 said:

They're coming out imminently. Next few months. That being said they're not likely consumer level devices, more devices meant for high scale servers.

The benefit on the consumer side is using less lanes for existing devices. For example high end SSDs with full speed out of 2 lanes instead of 4. 20 PCIe 4.0 lanes will be easier to implement than 40 PCIe 3.0 lanes.

Its not hard to implement craploads of lanes. Look at AMD naples, 128 Gen3 lanes per CPU.... 128.

[Sniperfox47]

7 hours ago, Prysin said:

Its not hard to implement craploads of lanes. Look at AMD naples, 128 Gen3 lanes per CPU.... 128.

Sure...? But the IOMMU on those lanes isn't as powerful, the lanes don't support advanced features like Virtual RAID, and are on an absolutely massive chip. EPYC starts at ~500mm^2 vs the intel chips where that's about as large as they get now. If it weren't for their infinity fabric interconnect scaling multiple dies it would be a completely unrealistic product, and even with it I'm worried what sort of performance they're going to get for DMI.

 

Doable and "not hard" are very very very different things. "Not hard" to do and "not hard" to do *well* are also very different things. Until we see EPYC on the market don't count your eggs about it's PCIe lanes.

[Agosto]

19 hours ago, Sniperfox47 said:

Sure...? But the IOMMU on those lanes isn't as powerful, the lanes don't support advanced features like Virtual RAID, and are on an absolutely massive chip. EPYC starts at ~500mm^2 vs the intel chips where that's about as large as they get now. If it weren't for their infinity fabric interconnect scaling multiple dies it would be a completely unrealistic product, and even with it I'm worried what sort of performance they're going to get for DMI.

 

Doable and "not hard" are very very very different things. "Not hard" to do and "not hard" to do *well* are also very different things. Until we see EPYC on the market don't count your eggs about it's PCIe lanes.

AGESA 1.0.0.6 fixed iommu for ryzen AFAIK, and keep in mind that that R7 and R5 are consumer products, unlike EPYC. Expect much better advanced features on that.

EPYC cpus are 4x ryzen dies (~200mm^2 each), not "a huge die". And biggest current intel CPUs are well over 500 mm^2. It's not important if it could have been done in a single die instead of interconnected dies, the important things are price, performance and power consumption. 

[Sniperfox47]

4 minutes ago, Agost said:

AGESA 1.0.0.6 fixed iommu for ryzen AFAIK, and keep in mind that that R7 and R5 are consumer products, unlike EPYC. Expect much better advanced features on that.

The IOMMU on Ryzen is an inherently simpler design though. It's not about the issues of Ryzen not fully supporting their IOMMU before, it's that the IOMMU inherently can't do some of the things the Intel one can.

 

6 minutes ago, Agost said:

EPYC cpus are 4x ryzen dies (~200mm^2 each), not "a huge die". And biggest current intel CPUs are well over 500 mm^2. It's not important if it could have been done in a single die instead of interconnected dies, the important things are price, performance and power consumption. 

I said exactly that. EPYC Chips are multiple dies and wouldn't be viable as a single large die.

 

Umm... High core count E7 are their biggest CPUs and the latest Broadwell-EX ones are 456.12mm^2

 

It's entirely important if it could be done on a single die, because a lot of server applications will be affected by the added latency of the interconnect. Infinity Fabric is a huge benefit for a lot of applications but is likely to hinder performance in a lot of others. Until we see EPYC in real-world use don't count your chickens with it.

[Agosto]

2 hours ago, Sniperfox47 said:

Umm... High core count E7 are their biggest CPUs and the latest Broadwell-EX ones are 456.12mm^2

With 10 less cores than EPYC. Moreover, AMD somehow managed to get high transistor and core density even with and inferior process (14nm LPP) which could make a hypotetical single die, 32c cpu smaller than intel's counterpart. For example, the 6950X chip has 3.4 billion transistors at about 250mm^2, while ryzen has 4.8 at ~200 mm^2 (some sources say 192mm^s, some 213 mm^2)

2 hours ago, Sniperfox47 said:

It's entirely important if it could be done on a single die, because a lot of server applications will be affected by the added latency of the interconnect. Infinity Fabric is a huge benefit for a lot of applications but is likely to hinder performance in a lot of others. Until we see EPYC in real-world use don't count your chickens with it.

 

As I said, performance is the key. If this desing leads to equal or better performance, it's a better option than a huge single chip. I'll wait for the benchmarks to see the actual behaviour of AMD's offering, but I'm pretty sure EPYC will be a seriously good competitor.

[Sniperfox47]

20 minutes ago, Agost said:

With 10 less cores than EPYC. Moreover, AMD somehow managed to get high transistor and core density even with and inferior process (14nm LPP) which could make a hypotetical single die, 32c cpu smaller than intel's counterpart. For example, the 6950X chip has 3.4 billion transistors at about 250mm^2, while ryzen has 4.8 at ~200 mm^2 (some sources say 192mm^s, some 213 mm^2)

I don't disagree with you there. I think Zen has great potential and I hope EPYC will be successful in, at the very least, niche applications so AMD can get some desperately needed revenue.

 

That being said, your point doesn't really disagree with anything I've said. A 32 core Zen based single die CPU may be smaller than a theoretical 32 core Broadwell-EX based CPU, but that doesn't really matter now does it? Fact is a single die EPYC wouldn't be viable cost wise, and likely wouldn't even be physically possible. Fact is a theoretical 32 core Broadwell-EX CPU definitely wouldn't be possible.

 

All I'm saying is that people seem to throw out EPYC as an example of an epic processor that wipes the floor with anything Intel has. Fact of the matter is that's unlikely and we won't know for sure one way or the other until we see it actually implemented. 

[Taf the Ghost]

1 hour ago, Sniperfox47 said:

I don't disagree with you there. I think Zen has great potential and I hope EPYC will be successful in, at the very least, niche applications so AMD can get some desperately needed revenue.

 

That being said, your point doesn't really disagree with anything I've said. A 32 core Zen based single die CPU may be smaller than a theoretical 32 core Broadwell-EX based CPU, but that doesn't really matter now does it? Fact is a single die EPYC wouldn't be viable cost wise, and likely wouldn't even be physically possible. Fact is a theoretical 32 core Broadwell-EX CPU definitely wouldn't be possible.

 

All I'm saying is that people seem to throw out EPYC as an example of an epic processor that wipes the floor with anything Intel has. Fact of the matter is that's unlikely and we won't know for sure one way or the other until we see it actually implemented. 

We won't know until people that really use the 1U and 2U systems give us deep feedback.  If the less consumer-based testing of Ryzen is anything to go by, it should do well. Some of the really high-end analytics guys said that, aside from 256-bit vector (so AVX2) calculation, the Zen core appears to be the most powerful currently available.  However, just because the core itself is incredibly good, it doesn't mean optimizations for it aren't going to be a large issue.  Since literally everything is tuned & optimized for Intel's key architecture, it's always a question if companies see enough of a reason to move over. (I also can't talk to issues with I/O and memory bandwidth, as Epyc will have 8 channel memory, which we can't replicate in testing on dual channel Ryzen.)

[Nicnac]

Y tho? Isn't 3.0 x16 still far away from being utilized at full bandwidth by consumer hardware?

[The Benjamins]

6 minutes ago, Nicnac said:

Y tho? Isn't 3.0 x16 still far away from being utilized at full bandwidth by consumer hardware?

for GPU's PCIe 3.0 x8 is enough but SSD's can saturate the x4 PCIe that is used for M.2.

also if the speed is faster it allows for more I/O with the same amount of lanes. example with a 16 lane CPU you can run 2 GPU's multiple PCIe SSD's and a 10Gbpe card if it was 4.0 but on 3.0 you would need more lanes.

[Nicnac]

2 minutes ago, The Benjamins said:

for GPU's PCIe 3.0 x8 is enough but SSD's can saturate the x4 PCIe that is used for M.2.

also if the speed is faster it allows for more I/O with the same amount of lanes. example with a 16 lane CPU you can run 2 GPU's multiple PCIe SSD's and a 10Gbpe card if it was 4.0 but on 3.0 you would need more lanes.

thanks for the info!

[JorAlv]

It will also be useful for Thunderbolt eGPU as it uses a 4x PCIe that isn't enough with PCIe 3.0 but will be fine with PCIe 4.0

[Sniperfox47]

3 hours ago, JorAlv said:

It will also be useful for Thunderbolt eGPU as it uses a 4x PCIe that isn't enough with PCIe 3.0 but will be fine with PCIe 4.0

Except thunderbolt 3 already has issues with broadcast distance that's why the cables are so short. If they made a version of thunderbolt using PCIe 4.0 that would be even worse.

 

The longest working cables for full speed Thunderbolt 3 are 1.6ft or 0.5m. with PCIe 4.0 you'd be lucky to see about half of that.

 

Until we start to see optical connections take off, Thunderbolt 3 is going to be stuck with PCIe 3.0 just due to cable lengths.

[The Benjamins]

4 minutes ago, Sniperfox47 said:

Except thunderbolt 3 already has issues with broadcast distance that's why the cables are so short. If they made a version of thunderbolt using PCIe 4.0 that would be even worse.

 

The longest working cables for full speed Thunderbolt 3 are 1.6ft or 0.5m. with PCIe 4.0 you'd be lucky to see about half of that.

 

Until we start to see optical connections take off, Thunderbolt 3 is going to be stuck with PCIe 3.0 just due to cable lengths.

The biggest cost for optical is the transceiver, lets hope they can do that it would be awesome.