AMD trims pricing of the Ryzen 7 1700 and 1700X: 1700 for $319, 1700X for $349.

[cj09beira]

1 minute ago, SpaceGhostC2C said:

At a completely different price point.

 

In any case, my point is that Ryzen hasn't been out long enough for AMD to panic, nor celebrate, whatever the current figures. Ryzen may be better value for your money than Intel for new buyers, but people who bought any of the most recent Intel architectures has a reason to run and sell their PCs and buy Ryzen. 

In other words, I don't think that a price change this early can be based on sales, whether high or low.

probably done to accommodate threadripper 

[captain cactus]

29 minutes ago, cj09beira said:

probably done to accommodate threadripper 

Which bodes well for those prices, actually. If AMD wants to have a low point of entry to 10 and 12-core CPUs then you don't want to price them too closely to consumer Ryzen because it'd cannibalise sales from either Ryzen (more powerful option isn't much more expensive) or Threadripper (slightly lower multi-core performance for a lot less money). 

[Curufinwe_wins]

I'm going to take a different stance here... 

 

This is pretty terrible news for AMD. Anytime you have to cannibalize the pricing of your products so soon after launch means you are underperforming expectations or you expect to coming up. Skylake-X is the likely culprit. 

 

Good for consumers though of course. 

[tom_w141]

1 hour ago, JoostinOnline said:

No they aren't.  Ryzen isn't a very good overclocker. You'll have to get lucky to push a 1700 to the same level as an 1800X. 

I know several people and have seen people on the forums with high OC 1700s and none with an 1800X that can hit 4.1GHz. Ryzen isn't a bad overclocker in fact its a great overclocker, at 4GHz my 1700 is overclocked >30%, the bad overclocker is the 1800X because AMD already overclocked it for you.

 

1 hour ago, djdwosk97 said:

That's not true at all. Basically all Ryzen chips will hit somewhere between 3.9-4.1ghz based on posts/reviews and the specific model doesn't seem to have much of an impact.

Exactly this.

[Sakkura]

24 minutes ago, ONOTech said:

Mmm, not necessarily. It could mean that they have so much product that they need to push them out quicker, so they lower the price.

 

If I remember correctly, the yields for the 8C CPUs are 80%. That's unbelievably high. I'm sure that definitely plays a part here.

 

They're probably also making room for ThreadRipper and preparing for Kaby Lake-X

That yield isn't exceptional and doesn't help them that much anyway, as they need to maintain the full product stack anyway.

[Belgarathian]

2 hours ago, djdwosk97 said:

So it only has single channel memory? 

I'm pretty sure it's been said that the R3 would be the same dual CCX design as the R5/R7. A single CCX die would also only a support single channel of RAM. 

Pretty sure they've already confirmed the R3 is a dual CCX with 2 cores disabled on both CCX. 

[Drak3]

11 minutes ago, Belgarathian said:

Pretty sure they've already confirmed the R3 is a dual CCX with 2 cores disabled on both CCX. 

I don't believe anything is actually confirmed yet, beyond that the R3 lineup is supposed to maintain the dual CCX design, and that's subject to change as far as we're concerned.

It could very well be a 4+0 configuration, 2+2, or both. It really depends on what, if any, faults are with each CCX. It could very well be that X% of R3's are 4+0 because on CCX has defunct cores, and that the rest are 2+2  because both CCX's have defunct cores (probably totaling 3), and that the first set become R3 1XXX, and the second become R3 1YYY.

[Belgarathian]

11 minutes ago, Drak3 said:

I don't believe anything is actually confirmed yet, beyond that the R3 lineup is supposed to maintain the dual CCX design, and that's subject to change as far as we're concerned.

It could very well be a 4+0 configuration, 2+2, or both. It really depends on what, if any, faults are with each CCX. It could very well be that X% of R3's are 4+0 because on CCX has defunct cores, and that the rest are 2+2  because both CCX's have defunct cores (probably totaling 3), and that the first set become R3 1XXX, and the second become R3 1YYY.

I think you'll find that R3 will have dual CCX with equal cores on either side so there is limited variation of performance between processors (latency for data between CCX). They'll keep dual CCX on the processors to ensure consistent architecture across the Ryzen range so that developers don't have to optimise for different variants. 

 

It will be interesting to see if they keep SMT on R3 as they've allowed OC on all CPUs to date. If they do keep SMT enabled, then I would imagine the R3 lineup will start with mid 2GHz targeting low-power applications (NAS/Display Signage/ATMs, etc) and the top R3 will be 3.1GHz 4c/8t just below the bottom R5. 

 

Single CCX variations may become APUs. 

[Drak3]

7 minutes ago, Belgarathian said:

It will be interesting to see if they keep SMT on R3 as they've allowed OC on all CPUs to date

Speculation is that they won't. The R3 will be equivalent to an i5, outside of OC potential.

 

7 minutes ago, Belgarathian said:

I think you'll find that R3 will have dual CCX with equal cores on either side so there is limited variation of performance between processors (latency for data between CCX). They'll keep dual CCX on the processors to ensure consistent architecture across the Ryzen range so that developers don't have to optimise for different variants.

It's entirely possible for AMD to produce different versions of the R3's with both 2+2 and 4+0, and keep them as separate models (or sub-lineups), in order to maximize usable chips.

A potential 4+0 R3 could be a 'Pro' version, and 2+2 being the standard and 'X' versions.

10 minutes ago, Belgarathian said:

Single CCX variations may become APUs

As per the plan, yes. Again, it's still up in the air as far as we're concerned. R3 and the APUs are taking alot longer to reach consumer hands than the R5 and R7 (and probably Threadripper and Epyc), so it is possible that something changed.

[leadeater]

6 hours ago, djdwosk97 said:

So it only has single channel memory? 

I'm pretty sure it's been said that the R3 would be the same dual CCX design as the R5/R7. A single CCX die would also only a support single channel of RAM. 

Single channel memory on an APU sounds like a horrible idea, unless there is on chip small GPU cache or something to compensate for the loss in bandwidth.

[leadeater]

6 hours ago, Drak3 said:

A potential 4+0 R3 could be a 'Pro' version, and 2+2 being the standard and 'X' versions.

AMD stated at one point, but I forget when/where, that all chips will be balanced so they won't do a 4+0. It may not be possible to actually disable all cores in a CCX due to the L3 cache design, who knows but you also don't want to have such a product design variation, Pro sub version or not.

 

And there isn't any reason to do a 4+0 design anyway. The cross CCX communication isn't as big of a problem as being made out and all the significant ones we know of so far have been patched.

[Taf the Ghost]

2 hours ago, leadeater said:

Single channel memory on an APU sounds like a horrible idea, unless there is on chip small GPU cache or something to compensate for the loss in bandwidth.

I've seen some people a little bummed there isn't 1Gb of HMB on the APU, so there's going to be access to cache issues for the Raven Ridge. 

 

As for the 1700X, this doesn't surprise me. The 1700 was just too good of a deal compared to the 1700X.  The Ryzen 7 stack is binned, slightly. 1800X tends to OC better than the 1700, on average.  (Though, it should be reminded, that a very small amount of people actually OC their CPUs.)   So the cost effectiveness of the 1700 over the other two was a bit much, so it's not that surprising that they'd drop the channel cost of the 1700X. But, for the bargain bin hunter, finding combos with the 1700X at the same price or lower than the 1700 are good.

[Scruffy90]

That didn't take long.

[Drak3]

1 minute ago, leadeater said:

And there isn't any reason to do a 4+0 design anyway. The cross CCX communication isn't as big of a problem as being made out and all the significant ones we know of so far have been patched.

Communication between CCX modules isn't the only reason that one could do a 4+0 configuration, it's actually an extremely weak reason. Should a sizeable portion of chips have faults on one CCX that prevent a 2+2 configuration, I'd rather see some 4+0 chips than none at all, even if they become a lesser variant due to cache limitations or making them a line independant of the main R3 round up.

 

5 minutes ago, leadeater said:

AMD stated at one point, but I forget when/where, that all chips will be balanced so they won't do a 4+0.

They also said that Polaris wasn't getting new chips after the RX 400 series. Threadripper wasn't planned for most of the R&D of Zen, as per AMD's roadmap. Right now, their official statements don't mean much, until we have product in our hands.

8 minutes ago, leadeater said:

It may not be possible to actually disable all cores in a CCX due to the L3 cache design, who knows but you also don't want to have such a product design variation, Pro sub version or not.

It is possible to disable a single CCX in Ryzen(ASUS boards might have downcore options that provide both the 2+2 and 4+0 option, depending on BIOS version), and 4+0 performs either identically, or slightly better, than 2+2, depending on the scenario. Either way, 4+0 is just as viable as 2+2.

 

https://www.techpowerup.com/231873/amd-ryzen-quad-core-2-2-vs-4-0-core-distributions-compared

[suits]

I love my Ryzen 1700. But I think they should axe the 1700 make the 1700x $300 and the 1800x $375. They are all 3 just similar. Before my 1700 I had a 1700x that clocked lower than my 1700 now does. Which is also the same as an 1800x (sometimes the 1800x gets to 4.1 GHz). 

[Taf the Ghost]

Just now, suits said:

I love my Ryzen 1700. But I think they should axe the 1700 make the 1700x $300 and the 1800x $375. They are all 3 just similar. Before my 1700 I had a 1700x that clocked lower than my 1700 now does. Which is also the same as an 1800x (sometimes the 1800x gets to 4.1 GHz). 

I imagine the Zen+ chips will drop a SKU on the 8 core model.  It made sense from a product stack, though for the hyper technical it was a way to save some money.

[Agosto]

11 hours ago, Sakkura said:

That yield isn't exceptional and doesn't help them that much anyway, as they need to maintain the full product stack anyway.

The report was about 80%+ of Ryzen CPUs having all working cores, this means that a good chunk of R5s have 8 potentially functional cores.

 

This helps since the lower the bad cores, the better it gets for Threadripper and Naples, which are MCMs, and thus they can ship more EPYC 32C and threadripper 16C. EPYC is VERY important for AMD.

[leadeater]

6 hours ago, Drak3 said:

It is possible to disable a single CCX in Ryzen(ASUS boards might have downcore options that provide both the 2+2 and 4+0 option, depending on BIOS version), and 4+0 performs either identically, or slightly better, than 2+2, depending on the scenario. Either way, 4+0 is just as viable as 2+2.

Would have to be a very low end SKU to go with disabling a CCX though, would mean half the L3 cache and single channel memory. Not that there wouldn't be uses for such a CPU: Low end NAS's, Thin Clients, Embeded system controllers etc. Can think of a lot of uses for such a CPU but probably not much more than a high end tablet or an actually usable netbook.

[Sakkura]

4 hours ago, Agost said:

The report was about 80%+ of Ryzen CPUs having all working cores, this means that a good chunk of R5s have 8 potentially functional cores.

 

This helps since the lower the bad cores, the better it gets for Threadripper and Naples, which are MCMs, and thus they can ship more EPYC 32C and threadripper 16C. EPYC is VERY important for AMD.

High yield may help later, yes, though the yield of their Ryzen silicon doesn't translate directly to yields for Threadripper/Naples.

 

But it doesn't really help AMD now, that a lot of Ryzen 5's could have been 7's. Just like it doesn't help Intel that lots of Core i5s could have been i7s and so on across their product stack.

[79wjd]

11 minutes ago, Sakkura said:

High yield may help later, yes, though the yield of their Ryzen silicon doesn't translate directly to yields for Threadripper/Naples.

 

But it doesn't really help AMD now, that a lot of Ryzen 5's could have been 7's. Just like it doesn't help Intel that lots of Core i5s could have been i7s and so on across their product stack.

It more or less does since Threadripper/Epyc is just multiple (2/4) R7 dies. 

 

And he was refuting your comment that "the yield isn't exceptional".

[Sakkura]

1 minute ago, djdwosk97 said:

It more or less does since Threadripper/Epyc is just multiple (2/4) R7 dies. 

 

And he was refuting your comment that "the yield isn't exceptional".

But the yield isn't exceptional.

[JoeCoke]

You can get a 1700 for a glorious $299.99 on Amazon right now.

[Drak3]

5 hours ago, leadeater said:

Would have to be a very low end SKU to go with disabling a CCX though, would mean half the L3 cache and single channel memory.

No it wouldn't. You can completely disable the cores of the CCX, and leave an IMC and cache intact, though the second point is moot, the R3 lineup is supposedly equipped with only 8MB of cache.

 

5 hours ago, leadeater said:

Can think of a lot of uses for such a CPU but probably not much more than a high end tablet or an actually usable netbook.

An R3 can fit any role that a stock/slightly OC'd Haswell i5 can.

[cj09beira]

i really dont think amd would use a 8 core die for the R3 segment, the demand for that market is too large, i believe they might use the ryzen mobile die with disabled graphics 

[cj09beira]

13 hours ago, leadeater said:

AMD stated at one point, but I forget when/where, that all chips will be balanced so they won't do a 4+0. It may not be possible to actually disable all cores in a CCX due to the L3 cache design, who knows but you also don't want to have such a product design variation, Pro sub version or not.

 

And there isn't any reason to do a 4+0 design anyway. The cross CCX communication isn't as big of a problem as being made out and all the significant ones we know of so far have been patched.

but if as i believe R3 is the same die as the apu's they probably have the ability to have 2 channel memory, in the ryzen 7 die it only has one memory channel per ccx, but it might be different in the apus, and probably will as apus need lots of bandwidth