AMD ryzen 80% have 8 working cores

[leadeater]

2 hours ago, mariushm said:

Probably wording is bad but just to clarify... as far as I know, the server processors are basically 4 ryzen dies, so there are 8 core complexes in a processor, each core complex with 4 cores and 4 threads. So overall, you have 4 times everything :  4 x 2 channel ddr4 x 2 slots per channel = 8 channel ddr4 x 2 slots per channel = 16 slots of memory , 8 x 8 MB L3 cache = 64 MB L3 cache , 8 x 2 MB L2 cache = 16 MB L2 cache , 4 x ~ 44 pci-e v3.0 links = ~ 128 pci-e links ... everything is 4x , simple as that. ..

 

I assume there's some optimizations and maybe some lower frequencies / smaller boosts in order to get these processors to use as little as 180 watts (TDP , which would work out to 45w TDP for each 8 core section - consider that when Ryzen 7 1700 is a 65w TDP part.  They may save some power by disabling the SOC part (sata controllers, usb 3.0 controllers) from a few of the modules and in order to reduce pin count on the socket ( a bit hard to have 4 x 6 sata3 and 4x2 usb 3.0 and so on, lots of extra pins and no sense wasting those pci-e v3.0 x4 lanes when they could expose them instead so people would plug SAS / hardware raid cards )

CCX is 4 cores 8 threads.

[Jito463]

@mariushm @leadeater

I don't think so.  If you look closely at a delidded Ryzen chip, you can see the split between the two sets of 4 cores.

 

Spoiler

 

Whereas, if you look at the picture of the delidded Epyc chip from the reveal, there's no apparent split in each of the CCX's.

 

Spoiler

I'm pretty sure Epyc (and Threadripper, by extension) use an octa core CCX, and aren't just recycling the quad core CCX's from Ryzen.

[Valentyn]

12 minutes ago, Jito463 said:

@mariushm @leadeater

I don't think so.  If you look closely at a delidded Ryzen chip, you can see the split between the two sets of 4 cores.

 

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Whereas, if you look at the picture of the delidded Epyc chip from the reveal, there's no apparent split in each of the CCX's.

 

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I'm pretty sure Epyc (and Threadripper, by extension) use an octa core CCX, and aren't just recycling the quad core CCX's from Ryzen.

That's a split in the solder, it looks like two solder pads were used.
 

That's also not a CCX, that's the full die. The two CCXs are seen here on the die shot.

As you can see two CCXs of 4 cores each, make up the rectangular die of the entire 8 core Zen.

 

 

[Jito463]

2 minutes ago, Valentyn said:

That's a split in the solder, it looks like two solder pads were used.
 

That's also not a CCX, that's the full die. The two CCX is seen here on the die shot.

As you can see two CCXs of 4 cores each, make up the rectangular die of the entire 8 core CPU.

 

 

Hmm, possibly.  I suppose we'll just have to wait and see.  As for CCX vs die, semantics.

[Valentyn]

6 minutes ago, Jito463 said:

Hmm, possibly.  I suppose we'll just have to wait and see.  As for CCX vs die, semantics.

Not semantics at all really, as the last image is straight from the International Solid-State Circuits conference detailing it all.

The CCX is part of the Die, it's not the complete item. As you can see each CCX has a single memory controller; meaning if it was the complete die, it would have single channel memory. Ryzen has Dual channel, Naples has 8 channel. It all lines up rather well.

 

Here's another image of delidded ryzen with most of the solder removed. No split in the rectangular die; but you can see the solder in the back on the lid having a split from the two pads he removed.
 

 

A video of Der8auer working on it more, no split seen at all.
 

 

[leadeater]

@Valentyn @Jito463

Correct, a CCX is an intentional design feature by AMD to have a scalable architecture and is part of a complete die but is not one itself. This allows AMD to deploy as many CCX's as required to get the configuration they want, in pairs from what it seems.

 

You can work out the number of CCX's in a given design by the number of memory channels supported, Threadripper is 4 channels so 4 CCX's and Naples is 8 channels so 8 CCX's. This also means that lower core SKUs that could use less CCX's won't be doing so just like with Ryzen 5, all Naples are 8 channel so will have 8 CCX's even if half the cores are disabled.

 

One of the key reasons for this I suspect is the Infinity Fabric which while is fast would likely hit some serious limitations if you have 8 cores worth of traffic using it versus 4 cores. A Naples chip deploying 8 core CCX's would have half the internal bandwidth of a 4 core CCX, not a problem if you never traverse the Infinity Fabric but in a server workload this is much more likely. Think about virtualization workloads where the hypervisor assigns VM cpu to any given core at any one time so a 4 core VM could have each vCPU on 4 different CCX's, now this sounds worse than a 8 core CCX configuration until you scale that out to 20-30 running VMs on that server which is where you want those extra Infinity Fabric interconnects.

[mariushm]

The infinity fabric is 256 bit wide bi-directional bus running at DDR4 frequency (minimum 1066 Mhz when DDR3 2133 Mhz are used) so with 8 DDR4 channels (8 x 64 bit = 512 bit) I imagine memory transfers from DDR4 memory to CPU would be quite nice.

 

Also, I guess they're going to use NUMA and applications that are aware of NUMA (like x265 for example) will be able to split data into jobs for each [1/2] core complexes and their caches and keep transfers between core complexes to as little as possible, so the infinity fabric won't be busy transferring data between two core complexes' level 3 caches

 

 

 

[Kamina]

AMD is the Heisenberg for making great silicon. 

[Jito463]

2 minutes ago, Kamina said:

AMD is the Heisenberg for making great silicon. 

I read that and had to do a double-take.  I thought you wrote Hindenburg. 

[leadeater]

5 hours ago, Jito463 said:

I thought you wrote Hindenburg.

Bulldozer, anyone? 

[Maticks]

On 2017-5-21 at 4:40 AM, Jito463 said:

I read that and had to do a double-take.  I thought you wrote Hindenburg. 

Helium filled processors..

[Dylanc1500]

23 minutes ago, Maticks said:

Helium filled processors..

Try hydrogen. It goes boom.

 

At least they could say it went out with a bang.

[Bananasplit_00]

On 2017-05-19 at 5:12 PM, TheNeonWhiteOne said:

AMD Enjoying High Yields For Zen Based Processors – More Than 80% Of Dies Have All 8 Cores Fully Operational

http://wccftech.com/amd-zen-yields-80-all-8-cores-functional/

 

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"According to a report from Bitsandchips.it, they are currently enjoying yields upwards of 80% which basically means that more than 80% of the Zen dies fabricated have all 8 cores fully functional."

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"Since the yields are above 80%, this means that the company will be able to increase in profits in two ways: either by decreasing the ASP (Average Selling Price) of the derivative products and shipping more volume and therefore larger profit, or, by simply increasing its profit margin on the products and keeping price the same. Looking at AMD’s core philosophy however, we may expect the silicon giant to go with the former approach and drop ASP all round. This means that products such as Naples which employ more than 1 core will also see a proportional ASP drop."

It would be nice if amd lowers ryzen prices. But mostly I am wondering how possible it would be to enable the disabled cores in r5s that would essentially turn them into an r7s. like enabling the extra 4gb in 4gb rx 480s or turning a 480 into a 580. Would it be possible and if so how would it be done.

the cores are more then likely physicaly severd and killed off, there is no flashing that.

[Jito463]

5 minutes ago, Bananasplit_00 said:

the cores are more then likely physicaly severd and killed off, there is no flashing that.

While I agree that's the most likely scenario, the fact is that we don't know for sure.  In the past, AMD has used software/firmware methods to disable cores, and it's possible they may have done so again.  I don't believe that's true, but I do acknowledge it's possible.

[TheNeonWhiteOne]

8 minutes ago, Bananasplit_00 said:

the cores are more then likely physicaly severd and killed off, there is no flashing that.

i assumed there was a way they could make sure cores couldn't be re enabled. thank you for the information. 

[Bananasplit_00]

14 minutes ago, Jito463 said:

While I agree that's the most likely scenario, the fact is that we don't know for sure.  In the past, AMD has used software/firmware methods to disable cores, and it's possible they may have done so again.  I don't believe that's true, but I do acknowledge it's possible.

thats for GPUs, im prettys sure there isnt a single case where you have been able to flash your CPU, at all.

12 minutes ago, TheNeonWhiteOne said:

i assumed there was a way they could make sure cores couldn't be re enabled. thank you for the information. 

basically jamming an exact knife into the working ones, but on a smaller level

[Sauron]

Lower the prices? They're already dirt cheap compared to Intel's offerings...

 

As for enabling extra cores, back in the phenom days people would actually do that, some motherboards had a dedicated bios option to force all available cores to run. Perhaps it will be possible on ryzen too (but again, it would have to be through bios). Bear in mind that good yields and all cores being fully functional doesn't necessarily mean they have sufficient headroom to be stable with all of them unlocked, especially if overclocked.

[Sauron]

6 minutes ago, Bananasplit_00 said:

thats for GPUs, im prettys sure there isnt a single case where you have been able to flash your CPU, at all.

basically jamming an exact knife into the working ones, but on a smaller level

You can't "flash" them because they don't have a firmware in the same way a graphics card does, but there have been instances of cpus that could be forced to use more cores than they advertised.

[Bananasplit_00]

Just now, Sauron said:

You can't "flash" them because they don't have a firmware in the same way a graphics card does, but there have been instances of cpus that could be forced to use more cores than they advertised.

really? id love to read up on that, do you know what ones?

[Sauron]

2 minutes ago, Bananasplit_00 said:

really? id love to read up on that, do you know what ones?

http://www.cpu-world.com/info/AMD/Unlocking_cores_and_L3.html

 

K10 based athlons and phenoms were known to do that, there may be more that I don't know about.

[79wjd]

44 minutes ago, Sauron said:

Lower the prices? They're already dirt cheap compared to Intel's offerings...

TIL that AMD needs to pay people to use Ryzen. 

[Belgarathian]

On 5/20/2017 at 3:57 AM, mariushm said:

 

The Ryzen 5 and Ryzen 7 are made out of 2 CCX (core complex) , basically 2 modules of 4 cores each.  The six core chips have one core of each core complex disabled.

 

The Ryzen 3 will most likely be made using just ONE core complex and maybe with less amount of Level 3 cache , and with all four cores enabled, because taking out one core complex and some memory would make them much smaller in area, and being so much smaller in surface area more of them would fit into a round 20-30cm silicon wafer and therefore they'd be more profitable to make.

 

it simply takes 6-8 months for a silicon chip that's physically different than previous chips (the ones with 2 core complexes) to go through the manufacturing process, to be packaged in the form you're used to and then have different firmware (microcode) written for it (has to be different because there's only one core complex instead of two, and the caches would also work slightly differently because of this and so on).

From this version with only one core complex and a maximum of 4 cores, they may make 3 core and 2 core processors (for the very cheapest models).

The most perfect chips from this production (the ones that can reach high frequencies at very low voltages may also be set aside to be made into laptop processors, because they'd be the most power efficient.

So because a part of the production is set aside , it may explain why they have to delay and make stock of these processors. Keep in mind that these will also be the most volume, they'll sell A LOT of them but with small profits per unit.

Nope, they've already confirmed it's using 2 CCXs with two cores disabled on either side. Reason being is for consistency across Ryzen 3, 5, 7, and EPYC so that developers only have to optimise for 1 architecture. Smart move. 

[leadeater]

1 hour ago, Belgarathian said:

Nope, they've already confirmed it's using 2 CCXs with two cores disabled on either side. Reason being is for consistency across Ryzen 3, 5, 7, and EPYC so that developers only have to optimise for 1 architecture. Smart move. 

And each CCX is tied to a memory channel looking at the die diagrams so if you went with 1 CCX it would be single channel CPU.

[JoostinOnline]

I bought some AMD stock after dumbass investors abandoned ship because they thought that the quarterly report would be super high because Ryzen 7 had just come out.  So this is good to hear.

[mariushm]

2 hours ago, Belgarathian said:

Nope, they've already confirmed it's using 2 CCXs with two cores disabled on either side. Reason being is for consistency across Ryzen 3, 5, 7, and EPYC so that developers only have to optimise for 1 architecture. Smart move. 

 

52 minutes ago, leadeater said:

And each CCX is tied to a memory channel looking at the die diagrams so if you went with 1 CCX it would be single channel CPU.

 

Yeah, it makes sense. 

 

Who knows, maybe we'll see some low end processors with just one CCX and one memory channel, like how the AM1 processors are.

 

I'd actually love to see AMD make a cpu with one CCX and integrated graphics and with 4 or 8 GB of HBM2 memory on die and NO other memory controllers, no option for adding ddr4 .. imagine how much space you'd save by not having those traces and wide slots. Dropping the ddr4 memory controller would also save power, so it wouldn't be hard to see it as a 15w-35w tdp processor.

Would make for some nice cpu to passively cool and make cool things in itx format... cpu socket, m.2 header, one pci-e for optional video card, usb 3.0 and sata in cpu.. tiniest of chipsets to add some usb 2.0 and bios and to support all the legacy crap.