What are the characteristics for Field Programmable Gate Arrays ?

[kynix]

I read an electronic magazine in which there is a report on the characteristics for field programmable gate arrays. After reading, I became interested in this topic, so I searched some materials and information about it, but found that it is not specific at all. Today I come to this forum to turn to you to discuss my understandings are appropriate.

 

Here are my personal understandings:

 

Field-programmable gate array (FPGA) is a programmable logic device, composed of thousands of exactly the same programmable logic unit, surrounded by the input / output unit composed of peripherals. It uses advanced computer-aided design technology for device development and design, its superiority far more than ordinary TTL integrated gate. Once the manufacturing is complete, the FPGA can be programmed at the job site to enable specific design functions.

 

 

 

As to this question, what are the characteristics for field programmable gate arrays, I have my personal points of views:

 

FPGA uses a new concept of logic cell array LCA (Logic Cell Array), including the configurable logic module CLB (Configurable Logic Block), output input module IOB (Input Output Block) and internal connection (Interconnect) three parts. The basic features of FPGA are:
1) FPGA design ASIC circuit, the user does not need to chip production, you can get a combination of chips. - 2) FPGA can do all other custom or semi-custom ASIC circuit of the sample sample.
3) FPGA has a rich internal trigger and I / O pin.
4) FPGA is the ASIC circuit design cycle of the shortest, the lowest cost of development, the risk of one of the smallest devices.
5) FPGA using high-speed CHMOS process, low power consumption, and CMOS, TTL level compatible.

 

It can be said, FPGA chip is a small batch system to improve system integration, reliability, one of the best choice.

 

Design, Implementation and Verification of Field Programmable Gate Array

 

The design input is the logical relationship to be implemented in the way that the development system supports the input computer, which is the beginning of designing the FPGA. There are several ways to achieve design input, the most commonly used schematic editor. It allows design input in two ways:

1) Graphic input This input mode allows the use of various conventional gate circuits and logic components (macrocell) provided in the component library to design the circuit and input it in schematic mode;
2) Text input This input method allows the use of advanced programmable logic design language, such as VHDL, ABEL, CUPL language to write input files, but also allows the direct use of Boolean equations for input.

The purpose of the design input is to generate an XNX (Xilinx Netlist Format) file, which is the design implementation and design validation of the input file. If both graphical input and text input are used, then merge (XNFMERGE) processing is required to produce a complete XNF file.

Design implementation is the core of the design and development process, the main task is to merge the XNF file segmentation, layout and wiring. Segmentation is to XNF file in the logic design through the simplified, split into CLB and I / OB as the basic unit of the logic design. The layout is to assign the split logical design to the corresponding CLB and I / OB positions of the FPGA. Wiring is a good layout of the CLB, I / OB connection. Xilinx development software with automatic layout, cabling function, it can be in the layout, wiring process using a series of optimization procedures to find the best layout, wiring program. The ultimate goal of the design implementation is to produce a bitstream file that meets the design requirements. This is used to load binary files for FPGA chips.

Design verification is mainly for the circuit simulation test. Simulation tests include functional simulation and real-time simulation. The functional simulation assumes that the signal produces the same delay time (0.1 ns) through each logic gate and that there is no delay through the path. This simulation can test whether the system function meets the design requirements. Real-time simulation is carried out after the layout and routing, it can be selected in accordance with the actual delay time of the device simulation, mainly used to verify the timing of the system.

Design input, design implementation and design verification of the three parts alternately, and finally to fully meet the design requirements of the binary file. With this file by loading the cable or programming EPROM FPGA load, you can get the user needs ASIC chip.

 

Developing trend for Field Programmable Gate Array

 

With the development of microelectronics, EDA technology, and application system requirements, FPGAs are becoming a platform for digital system development and will continue to improve and improve in the following areas:
(1) high integration, high capacity, low cost, low voltage, low power consumption;
(2) resource diversification;
(3) for on-chip systems: processors, high-speed serial I / O, DSP, etc.;
(4) the use of deep submicron processes. Currently based on 90nm process FPGA has been commercial, is to advance to 65nm;
(5) the development and improvement of various soft and hard IP library;
(6) dynamic reconfigurable technology practical.

 

Ps: Excuse me if I was wrong in words or expressions as I am a green hand in the field of FPGAs. I need continual learnings.

 

What is your idea ? Do you agree with my ideas ? Any of your ideas would be highly appreciated.

 

May someone would like to help ?

 

thanks in advance.

 

 

[Mira Yurizaki]

12 hours ago, kynix said:

FPGA uses a new concept of logic cell array LCA (Logic Cell Array), including the configurable logic module CLB (Configurable Logic Block), output input module IOB (Input Output Block) and internal connection (Interconnect) three parts.

This irks me. This isn't a new concept at all. I've played with FPGAs 10 years ago in college (*sigh* now I feel old) and one of my labs was to make a Pong clone.

[kynix]

Why do you say that it is not a new concept ? thanks in advance.

[imreloadin]

On 4/5/2017 at 10:41 PM, kynix said:

Why do you say that it is not a new concept ? thanks in advance.

Probably because he said he used that same thing 10 years ago...which considering how well technology ages it's pretty much ancient at this point.

[kynix]

Ok, I have got your meanings. I think that you can use the concept for more than 10 years or even longer. That is above the boundaries.