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Ryzen CoreInfo

I was looking at sysinternals' CoreInfo program, and something caught my eye that made me curious:
 

Quote


Logical to Physical Processor Map:
**----  Physical Processor 0 (Hyperthreaded)
--**--  Physical Processor 1 (Hyperthreaded)
----**  Physical Processor 2 (Hyperthreaded)

Logical Processor to Socket Map:
******  Socket 0

Logical Processor to NUMA Node Map:
******  NUMA Node 0

No NUMA nodes.

Logical Processor to Cache Map:
...

Logical Processor to Group Map:
******  Group 0

 

 

If anyone with a Windows/i7 or a Windows/Ryzen system could check what the logical processor to group map is on their computers, I'd be interested in seeing that, given the hubub about core complexes on Ryzen.

 

I'm on an AMD FX 6300, for what it's worth.

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Spoiler

 

Maximum implemented CPUID leaves: 0000000D (Basic), 80000008 (Extended).

Logical to Physical Processor Map:
**------  Physical Processor 0 (Hyperthreaded)
--**----  Physical Processor 1 (Hyperthreaded)
----**--  Physical Processor 2 (Hyperthreaded)
------**  Physical Processor 3 (Hyperthreaded)

Logical Processor to Socket Map:
********  Socket 0

Logical Processor to NUMA Node Map:
********  NUMA Node 0

No NUMA nodes.

Logical Processor to Cache Map:
**------  Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64
**------  Instruction Cache   0, Level 1,   32 KB, Assoc   8, LineSize  64
**------  Unified Cache       0, Level 2,  256 KB, Assoc   8, LineSize  64
--**----  Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64
--**----  Instruction Cache   1, Level 1,   32 KB, Assoc   8, LineSize  64
--**----  Unified Cache       1, Level 2,  256 KB, Assoc   8, LineSize  64
----**--  Data Cache          2, Level 1,   32 KB, Assoc   8, LineSize  64
----**--  Instruction Cache   2, Level 1,   32 KB, Assoc   8, LineSize  64
----**--  Unified Cache       2, Level 2,  256 KB, Assoc   8, LineSize  64
------**  Data Cache          3, Level 1,   32 KB, Assoc   8, LineSize  64
------**  Instruction Cache   3, Level 1,   32 KB, Assoc   8, LineSize  64
------**  Unified Cache       3, Level 2,  256 KB, Assoc   8, LineSize  64
********  Unified Cache       4, Level 3,    8 MB, Assoc  16, LineSize  64

Logical Processor to Group Map:
********  Group 0

 

This is a i7-2600

if you want to annoy me, then join my teamspeak server ts.benja.cc

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Here ya go.  1800x

Spoiler

 

AMD Ryzen 7 1800X Eight-Core Processor
AMD64 Family 23 Model 1 Stepping 1, AuthenticAMD

 

Logical to Physical Processor Map:
**--------------  Physical Processor 0 (Hyperthreaded)
--**------------  Physical Processor 1 (Hyperthreaded)
----**----------  Physical Processor 2 (Hyperthreaded)
------**--------  Physical Processor 3 (Hyperthreaded)
--------**------  Physical Processor 4 (Hyperthreaded)
----------**----  Physical Processor 5 (Hyperthreaded)
------------**--  Physical Processor 6 (Hyperthreaded)
--------------**  Physical Processor 7 (Hyperthreaded)

Logical Processor to Socket Map:
****************  Socket 0

Logical Processor to NUMA Node Map:
****************  NUMA Node 0

No NUMA nodes.

Logical Processor to Cache Map:
**--------------  Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64
**--------------  Instruction Cache   0, Level 1,   64 KB, Assoc   4, LineSize  64
**--------------  Unified Cache       0, Level 2,  512 KB, Assoc   8, LineSize  64
********--------  Unified Cache       1, Level 3,    8 MB, Assoc  16, LineSize  64
--**------------  Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64
--**------------  Instruction Cache   1, Level 1,   64 KB, Assoc   4, LineSize  64
--**------------  Unified Cache       2, Level 2,  512 KB, Assoc   8, LineSize  64
----**----------  Data Cache          2, Level 1,   32 KB, Assoc   8, LineSize  64
----**----------  Instruction Cache   2, Level 1,   64 KB, Assoc   4, LineSize  64
----**----------  Unified Cache       3, Level 2,  512 KB, Assoc   8, LineSize  64
------**--------  Data Cache          3, Level 1,   32 KB, Assoc   8, LineSize  64
------**--------  Instruction Cache   3, Level 1,   64 KB, Assoc   4, LineSize  64
------**--------  Unified Cache       4, Level 2,  512 KB, Assoc   8, LineSize  64
--------**------  Data Cache          4, Level 1,   32 KB, Assoc   8, LineSize  64
--------**------  Instruction Cache   4, Level 1,   64 KB, Assoc   4, LineSize  64
--------**------  Unified Cache       5, Level 2,  512 KB, Assoc   8, LineSize  64
--------********  Unified Cache       6, Level 3,    8 MB, Assoc  16, LineSize  64
----------**----  Data Cache          5, Level 1,   32 KB, Assoc   8, LineSize  64
----------**----  Instruction Cache   5, Level 1,   64 KB, Assoc   4, LineSize  64
----------**----  Unified Cache       7, Level 2,  512 KB, Assoc   8, LineSize  64
------------**--  Data Cache          6, Level 1,   32 KB, Assoc   8, LineSize  64
------------**--  Instruction Cache   6, Level 1,   64 KB, Assoc   4, LineSize  64
------------**--  Unified Cache       8, Level 2,  512 KB, Assoc   8, LineSize  64
--------------**  Data Cache          7, Level 1,   32 KB, Assoc   8, LineSize  64
--------------**  Instruction Cache   7, Level 1,   64 KB, Assoc   4, LineSize  64
--------------**  Unified Cache       9, Level 2,  512 KB, Assoc   8, LineSize  64

Logical Processor to Group Map:
****************  Group 0

 

 

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Interesting!

 

Here's what I found about processor groups: https://msdn.microsoft.com/en-us/library/windows/desktop/dd405503(v=vs.85).aspx

 

TL;DR, they're designed to allow Windows to support more than 64 logical processors on a single computer (ie, server environments, supercomputers). Here's where it gets fun:

Quote

By default, an application is constrained to a single group, which should provide ample processing capability for the typical application.

...64 cores is kind of a lot...

 

It sounds like MS could use processor groups to fix a lot of Ryzen performance oddities in one fell swoop. The downside here is that if they turn Ryzen into a two-group CPU, applications will need to do their own thread affinity to cross the core complex divide, and that's probably not something AMD wants. Because of that, I suspect MS could find a better way to handle things.

 

Well, it'll be interesting to see what MS does, and hopefully readers of this thread find the topology choices interesting.

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