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AMD speaks on W10 scheduler and Ryzen

5 minutes ago, leadeater said:

That is actually a really good point and sounds plausible for why we can't change them.

this is why we need that fucking block diagram I keep searching for

if the MC is directly connected to the interconnect bus fabric .. good god!

 

here's what else strikes me as odd: on Kaby, the 2666 DDR4 has a latency of just 53ns compared to 90ns of Ryzen - that's almost double

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6 minutes ago, zMeul said:

this is why we need that fucking block diagram I keep searching for

if the MC is directly connected to the interconnect bus fabric .. good god!

 

here's what else strikes me as odd: on Kaby, the 2666 DDR4 has a latency of just 53ns compared to 90ns of Ryzen - that's almost double

If I could see the tertiary timings, I'd easily be able to tell you why. I can make 2666 C15 have god awful latency with a few simple tweaks, lol. 

My (incomplete) memory overclocking guide: 

 

Does memory speed impact gaming performance? Click here to find out!

On 1/2/2017 at 9:32 PM, MageTank said:

Sometimes, we all need a little inspiration.

 

 

 

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17 minutes ago, MageTank said:

If I could see the tertiary timings, I'd easily be able to tell you why. I can make 2666 C15 have god awful latency with a few simple tweaks, lol. 

[Intel] G.Skill Trident Z 2666MHz 16-16-16-36
[AMD] Corsair Vengeace LPX 2666MHz 16-16-16-36

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7 hours ago, zMeul said:

[Intel] G.Skill Trident Z 2666MHz 16-16-16-36
[AMD] Corsair Vengeace LPX 2666MHz 16-16-16-36

Those are the primary timings, not the tertiary timings. The primary timings actually mean very little to me when it comes to latency. 

My (incomplete) memory overclocking guide: 

 

Does memory speed impact gaming performance? Click here to find out!

On 1/2/2017 at 9:32 PM, MageTank said:

Sometimes, we all need a little inspiration.

 

 

 

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@leadeaterI fuckign found something really really interesting and explains why results are the way they are

I was correct to assume the data transfer is done through the fabric interconnect bus and L3 and not the L2

http://www.hardware.fr/articles/956-23/retour-sous-systeme-memoire.html

IMG0053311_1.jpg

 

this is vastly different on how Intel does it:

Intel-Skylake-Gen9-GPU.png

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1 hour ago, zMeul said:

@leadeaterI fuckign found something really really interesting and explains why results are the way they are

I was correct to assume the data transfer is done through the fabric interconnect bus and L3 and not the L2

http://www.hardware.fr/articles/956-23/retour-sous-systeme-memoire.html

 

this is vastly different on how Intel does it:

We've known for a long time Ryzen L3 cache is very different from Intel's, AMD has said it's a victim cache. See here for generic explanation of a victim cache: https://en.wikipedia.org/wiki/Victim_cache

 

This likely explains why they went with a victim cache over a fully function L3 cache though, since it is used for CCX data flows you can't leave it filled with instruction cache.

 

Nice find btw, great to actually see a diagram with detailed information in it or more than we have previously seen at least.

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