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AMD Zen server platform detailed

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1 minute ago, Prysin said:

no it cannot outmatch a GPU at the graphics (especially with mods) because memory bandwidth would be a limiting factor.

 

Yeah, you are right. Didn't think of it that way.

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9 hours ago, leadeater said:

There are two server architectures, Zeppelin (APU) (8c, 12c(?), 16c) and Naples (CPU) (16c(?), 24c and 32c). Keep in mind details about both of these all over the damn place with tons of contradicting details between sources and even from the same source, online news sites need to do a way better job at amending articles or taking them down when new information comes to light.

 

I've seen some say both are based off 8 core modules, multi chip package when required, and others saying Naples is 16 core modules, multi chip package when required. I guess both are viable but I'm going to bet on 16 core dies for Napples.

 

Multi chip package for a 24 core offering will be much cheaper using two 16 core dies than three 8 core dies or a single die (defect that invalidates the entire chip). Defective cores can be disabled when they fail to validate for use in a 16/32 core package where you would need 3 perfect 8 core dies or 1 large perfect die. I guess the chances of defects in a larger 16 core die is higher. Joining 2 dies in a single package is cheaper than 3, and less complex.

 

The down side to multi die packages is you lose cache coherency efficiency but there is still internal die separation between cores and cache, NUMA nodes. This exists in Intel processors and these AMD processors (from what I've read, 4 cores per node).

 

As these core counts are getting higher and process nodes getting smaller plus die size and complexity getting higher, or same size but more transistors, I think monolithic dies are becoming a worse choice than multi chip packages from a technical perspective and way more so from a business perspective (yields etc).

 

Huge dies and many cores are really complex and making full use of them is a challenge, easy in the virtualization world but this is an area were monolithic vs multi chip makes zero difference unless you assign more cores to a VM than a single chip module. This is already an issue anyway if you assign more than on a single CPU so no change here at all.

 

With an multi chip design you can focus on making each chip extremely efficient and make this design compiler and OS aware then just add dies to give the core/performance package required. Cross die-core communication still happens through L3 cache as it would in a monolithic die but instead of there being a single L3 cache there is L3 cache per die, this can also be a good thing since it will prevent a subset of cores stealing all L3 cache.

totally agree

and i hope that there will be a workstation board that supports this cpus. 

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