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NumLock21

Kaby Lake 7700K up for pre-order

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22 hours ago, ARikozuM said:

You'll be fine for 3-4 more years.

I know. But the board is hideous and and can't OC, so I'll probably be looking a a i7/i5-8000


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22 hours ago, Thorimus said:

*sigh* and here I am with a 3570K (on a H-series board no less) and no money to upgrade

no need to upgrade... im here on a 2600 and everything runs fine on it still.

 


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31 minutes ago, Thorimus said:

I know. But the board is hideous and and can't OC, so I'll probably be looking a a i7/i5-8000

I would just replace the board, then. Ebay has a few of them new.


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22 hours ago, Dabombinable said:

Which is kind of sad, though it is their fault for doing their usual "completely new architecture" trick with Bulldozer, and utterly failing after that. Lets just hope that Zen becomes K7 all over again-it beat the shit out of Pentium III with its far faster FPU.

All we can do is hope... They've had this long already xD


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2 minutes ago, TheRandomness said:

All we can do is hope... They've had this long already xD

Unfortunately for us we need shitloads, because AMD when they launched Piledriver in 2012, still had its high clocked variants (3GHz=) being worse than Harpertown which released in 2007.


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Just now, Dabombinable said:

Unfortunately for us we need shitloads, because AMD when they launched Piledriver in 2012, still had its high clocked variants (3GHz=) being worse than Harpertown which released in 2007.

I just need something that does better than an i7-5775c for a decent price... Let's hope, shall we?


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14 minutes ago, TheRandomness said:

I just need something that does better than an i7-5775c for a decent price... Let's hope, shall we?

That will probably be a while away-as in 4 years+, the way AMD has been going.


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1 hour ago, VerticalDiscussions said:

So, who has already pre-ordered the I7-7700K xD?

Peasant, you should wait for the 7790K with 4.7GHz boost.


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21 hours ago, patrickjp93 said:

 

Full H.265 10-bit encode and decode hardware acceleration. Even Nvidia and AMD don't have that yet.

Is it weird that I'm turned on by that :x

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Posted · Original PosterOP
16 hours ago, zMeul said:

the chipset doesn't have to support anything since the DDR4 controller is in the CPU 

 

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ad8469a37178c5e98c6324c2b7da2e93.jpg

 

That diagram is just showing the official max ram clock for DDR4 and DDR3L. Well, right now Kaby Lake specs isn't out yet,  don't know what their new official max ram clocks will be.


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4 hours ago, NumLock21 said:

That diagram is just showing the official max ram clock for DDR4 and DDR3L. Well, right now Kaby Lake specs isn't out yet,  don't know what their new official max ram clocks will be.

block diagram was for Skylake ;)

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On 18.9.2016 at 5:41 AM, patrickjp93 said:

single sample test of a piece of open-source software demonstrated by AMD under conditions that were easily manipulated and no one can verify

you have no idea how in favor of intel blender is , it is actually of of the things they use to show off the new stuff 

 

just sayn 


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On 18.9.2016 at 2:13 AM, patrickjp93 said:

http://www.agner.org/optimize/instruction_tables.pdf

 

When you come up with a way to make instructions execute in less than 1 cycle, feel free to tell Intel's engineers how incompetent they are. The amount of computational horsepower has doubled since Sandy Bridge per core along with clock boosts. The problem is software, not Intel.

this is a lot to read through , is there simpler version? 

 

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Just now, Space Reptile said:

this is a lot to read through , is there simpler version? 

 

(Graphs man GRAPHS)

It's an interesting bathroom read if it helps.


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Just now, ARikozuM said:

It's an interesting bathroom read if it helps.

true , sadly the tables are up to ~20 pages long , and i just dont know WHAT values to compare ( º _ º ) 


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Just now, Space Reptile said:

true , sadly the tables are up to ~20 pages long , and i just dont know WHAT values to compare ( º _ º ) 

 

2 minutes ago, ARikozuM said:

It's an interesting multi-trip bathroom read if it helps.

 


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1 hour ago, Space Reptile said:

you have no idea how in favor of intel blender is , it is actually of of the things they use to show off the new stuff 

 

just sayn 

No it's not. In fact it favors Solaris Architecture far more than it does x86.

 

The only way it can favor Intel is by, wait for it, having instruction paths that are up to date with Intel's newest instructions!

 

And Blender loves vector instructions, as it should. It's a heavily data-parallel application. AMD not having an independent vector unit per core hurts it in HPC applications. That is not the software makers giving Intel undue favor. That's just AMD sucking at something. And like I said, it's way too easy to manipulate that test. I don't buy it at all without 3rd party confirmation on the software as distributed by Git and SVN. Customized versions (I suspect AMD tailored the code to better optimize for its cache structure, which is only legitimate if that code is released to the main repository where it will actually affect all users) do not count.


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1 hour ago, Space Reptile said:

this is a lot to read through , is there simpler version? 

 

(Graphs man GRAPHS)

No. Take the latency tables from every architecture Nehalem going forward and compare instructions that work on 1 piece of data in a register. Almost all of them were reduced to 1-2 cycles way back then. And if data isn't in registers, we go to cache. Intel's been working on cache latency shaving. The cycles have fallen, but it'll never be as fast as data in registers. That is the problem. Intel is a victim of its own success. It's not slow in innovating. If software kept up, AMD would have died in 2012, because the performance increase you get by bringing in SIMD and MIMD instructions is 2,4, and even 8x.

 

I suppose I could make a graph when I get home, but seriously, I read this every time I go to optimize my C++ code and double-check the compiler's generated assembly. It's not that hard. If you want the nitty gritty stuff, you could read Intel's 4000 page x86 manual and optimization guide.


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7 hours ago, Space Reptile said:

true , sadly the tables are up to ~20 pages long , and i just dont know WHAT values to compare ( º _ º ) 

This is really only 1/4 of the story (instruction latencies, instruction throughputs, pipeline tweaks, and cache/memory system improvements), but this should give you a solid idea of what Intel is deciding to optimize where it can, and what's just at its limits or can be discarded because of diminishing use.

 

Bear in mind every one of the instructions I tabulated has an MMX, SSE1/2/3/4, or AVX1/2 counterpart with 2,4, or 8x the throughput, and even among the instructions listed, newer architectures can handle 2 or more of them per cycle. When you can't make the singletons go any faster, let there be groups of ever-increasing size. 

 

 

Instruction Latency Comparison.xlsx


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Posted · Original PosterOP
11 hours ago, zMeul said:

block diagram was for Skylake ;)

I know that's Skylake.


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