AMD Hosting Zen Event at HotChips on Tuesday

[DocSwag]

Source:http://www.hotchips.org/program/

Quote

5:45 PM	Processors	Inside 6th generation Intel Core code named Skylake:: New Microarchitecture and Power Management	Jack Doweck	Intel
		POWER9: Processor for the Cognitive Era	Brian Thompto	IBM
		A New, High Performance x86 Core Design from AMD	Michael Clark	AMD

So it seems that on Tuesday of this week at 5:45 P.M. AMD will be hosting an event on "A New, High Performance x86 Core Design from AMD." This is quite obviously Zen that they're talking about, so by the sounds of it it looks like we'll be getting more architectural details on the Zen architecture. This will definitely be an interesting follow up to the info AMD gave us a few days ago on the memory heirachy of Zen, and hopefully they'll give us more info on the design of the individual cores in Zen as well as perhaps some more benchmarks (though I personally am not betting on this happening). So stay tuned for more Zen coming at ya in 2 days!

[TheRandomness]

Tbh I'm more interested in that power9. I've read a bit about them but still

[Tech_Dreamer]

'HotChips' You say..

 

#Coincidence?

[Energycore]

4 minutes ago, Tech_Dreamer said:

'HotChips' You say..

 

#Coincidence?

The stigma will never die

[Rune]

17 minutes ago, CUDA_Cores said:

All I have to say about this is AMD, please launch Zen when you are ready. Do not pay attention to the hype over your CPUs and launch them ONLY when you are ready. Because intel isn't making any of their CPUs faster now anyways so you don't have to worry about catching up to some new and faster future CPU that doesn't even exist yet (because it will only be 0.3% faster than last-gen anyways).

0.3%? The fuck? What world are you living in? On top of the 7-10% improvements of each generation they've been tweaking pretty much everything else. While it is true that Intel has been focusing more on efficiency in the last four generations, its not like they've been sitting on ass doing nothing but releasing the same thing over and over. WIDI/WiGIG is amazeballs, having a 13-17 hour battery on a decent sized laptop would have been unheard of even two years ago, and even iGPUs have been getting massively better (though with the advent of e-GPUs this may not be a thing for much longer). AMD should indeed take their time to get this right, but they should have started aiming for this goal years before they did.

[NumLock21]

Quote Intel Omni-Path 4.8 Tbps Switch ASIC and PlatformJames KunzIntel

[Energycore]

3 minutes ago, Rune said:

0.3%? The fuck? What world are you living in? On top of the 7-10% improvements of each generation they've been tweaking pretty much everything else. While it is true that Intel has been focusing more on efficiency in the last four generations, its not like they've been sitting on ass doing nothing but releasing the same thing over and over. WIDI/WiGIG is amazeballs, having a 13-17 hour battery on a decent sized laptop would have been unheard of even two years ago, and even iGPUs have been getting massively better (though with the advent of e-GPUs this may not be a thing for much longer). AMD should indeed take their time to get this right, but they should have started aiming for this goal years before they did.

I will concede that 10% over 5 generations amounts to just over 60% improvement considering.

 

So Zen hitting Broadwell is highly unlikely. Haswell maybe.

[Rune]

Just now, Energycore said:

I will concede that 10% over 5 generations amounts to just over 60% improvement considering.

 

So Zen hitting Broadwell is highly unlikely. Haswell maybe.

I believe I do remember reading Haswell to be the more accurate comparison. That'd be great compared to what they have now, but I don't think it would be enough to cause the red party people seem to be preparing for.

[PRTI]

7 minutes ago, Energycore said:

I will concede that 10% over 5 generations amounts to just over 60% improvement considering.

 

So Zen hitting Broadwell is highly unlikely. Haswell maybe.

 CPU's can be hit?

 

I will probably hit me Pentium 3 up to go on a date  

[Rune]

1 minute ago, keNNySOC said:

 CPU's can be hit?

 

I will probably hit me Pentium 3 up to go on a date  

Pentium 3 was born in 1999.

[PRTI]

Just now, Rune said:

Pentium 3 was born in 1999.

Same year as my favorite game

[Energycore]

5 minutes ago, Rune said:

Pentium 3 was born in 1999.

Just wait 6 months before you bed Pentium and you're good.

[Ryujin2003]

6 minutes ago, Rune said:

Pentium 3 was born in 1999.

Was it Y2K proof?

[patrickjp93]

1 hour ago, CUDA_Cores said:

All I have to say about this is AMD, please launch Zen when you are ready. Do not pay attention to the hype over your CPUs and launch them ONLY when you are ready. Because intel isn't making any of their CPUs faster now anyways so you don't have to worry about catching up to some new and faster future CPU that doesn't even exist yet (because it will only be 0.3% faster than last-gen anyways).

My God where do you people keep coming from?! Intel makes its CPUs faster every year by mind-boggling amounts assuming you have programmers who can properly optimize code. Intel can't make 2 integers add together any faster than 1 cycle. No one can, yet that's what Intel would have to do for you people to feel it because software stagnated.

[That Norwegian Guy]

31 minutes ago, Energycore said:

Just wait 6 months before you bed Pentium and you're good.

Age of sexual consent is 16 or under in 95% of the world

 

Anywho, I'm interested to see what they're launching with (high or low SKU) to determine what yields they have. Hopefully they launch their higher-end CPUs first, which will mean high yields and they don't have to gather up bins for months to be able to supply higher end chips (and also more profit for fab and AMD)

[Notional]

45 minutes ago, Ryujin2003 said:

Was it Y2K proof?

Nothing was Y2K proof #Fallout4

---

 

That being said, this should be interesting. After all December is only 3 months away now (give or take a week), so we should start to see info about the finished product. Now give some AM4 news please.

[Energycore]

48 minutes ago, That Norwegian Guy said:

Age of sexual consent is 16 or under in 95% of the world

 

Anywho, I'm interested to see what they're launching with (high or low SKU) to determine what yields they have. Hopefully they launch their higher-end CPUs first, which will mean high yields and they don't have to gather up bins for months to be able to supply higher end chips (and also more profit for fab and AMD)

Assuming US/Canada because LTT

 

I think they'll launch the 8/16 Core First? Dunno

[Fetzie]

3 hours ago, Ryujin2003 said:

Was it Y2K proof?

I would hope so, I was using a Pentium 166 until 2002

[Tomsen]

4 hours ago, patrickjp93 said:

My God where do you people keep coming from?! Intel makes its CPUs faster every year by mind-boggling amounts assuming you have programmers who can properly optimize code. Intel can't make 2 integers add together any faster than 1 cycle. No one can, yet that's what Intel would have to do for you people to feel it because software stagnated.

Patrick, you're being foolish again.

Intel has increased the data parallism of its vector units by a good amount from each new architecture. Thats helps alots in certain workloads, and basically have no benefits outside it. Trying to defend it by saying "programmers who can properly optimize code" is stupid, you can't properly optimize all code (far from actually) to vector code and expect the same scalability. In the general pipeline outside of vector data parallelism, what have Intel exactly done to makes it CPU faster? Not much.

 

Also Intel have made a CPU who can make 2 integers add together faster than 1 cycle, ie. netburst. That is if you remember clock cycles are a relative.

[Ridska]

Dear AMD , I love you and all but please dont jack this one up. I have high hopes for this CPU, but that does not mean that you have to rush it through the door. Take as much as time you want , I want this to be near perfect.

[Citadelen]

6 hours ago, Nicholatian said:

IPC improvements are magnitudes greater than 0.3%, not to mention Intel has been gradually upping clock rates as well since Sandy Bridge.

Well Kabylake is just a Skylake refresh. It's nothing special, other than some beefier on-board graphics.

[patrickjp93]

14 minutes ago, Tomsen said:

Patrick, you're being foolish again.

Intel has increased the data parallism of its vector units by a good amount from each new architecture. Thats helps alots in certain workloads, and basically have no benefits outside it. Trying to defend it by saying "programmers who can properly optimize code" is stupid, you can't properly optimize all code (far from actually) to vector code and expect the same scalability. In the general pipeline outside of vector data parallelism, what have Intel exactly done to makes it CPU faster? Not much.

 

Also Intel have made a CPU who can make 2 integers add together faster than 1 cycle, ie. netburst. That is if you remember clock cycles are a relative.

I'm sorry but you're also forgetting MIMD instructions, and you'd be surprised how much of game code can be vectorized, especially if the engine is component based.

 

Also wrong. Steven Lavavej, Andrei Alendrescu, and Scott Meyers are all the proof you need.

 

Intel increased its independent execution port number to 9 and provided not 1,2, or 3 ALUs, but 4. At some point it comes down to programmers. We have SIMD, and we have MIMD. People need to get with the times or get out of the way.

 

No, Netburst did not. What it did do is introduce having 2 ALUs, making the throughput increase, but not decreasing the instruction latency.

[Valentyn]

5 hours ago, Notional said:

Nothing was Y2K proof #Fallout4

 

 

Including the game's performance and graphics

[Castdeath97]

AMD all I want is for the following three points to be achieved in the consumer CPU market, even partially:

 

1-Being able to get a proper quad under 180 USD with good IPC  (basically under the i5 4460/i5 6400)

2- Having a overclockable CPU under the 180 USD point that is half decent and is not a silly pentium that only overclock with Z97 after a stupid microcode update or a old FX/Athlon CPUs. 

3-Maybe we can get less pricey proper 6+ core CPUs

[Tomsen]

21 minutes ago, patrickjp93 said:

I'm sorry but you're also forgetting MIMD instructions, and you'd be surprised how much of game code can be vectorized, especially if the engine is component based.

 

Also wrong. Steven Lavavej, Andrei Alendrescu, and Scott Meyers are all the proof you need.

 

Intel increased its independent execution port number to 9 and provided not 1,2, or 3 ALUs, but 4. At some point it comes down to programmers. We have SIMD, and we have MIMD. People need to get with the times or get out of the way.

 

No, Netburst did not. What it did do is introduce having 2 ALUs, making the throughput increase, but not decreasing the instruction latency.

Name a few of those MIMD instructions then (just to make sure we are talking about the same things, I don't think you are through). Games sure have things that can be parallelized, the issue is rather the more serialized procedure dx11 takes. Let me frame it this way: Could the same optimizations not be done in scalar code and yield the same benefits?

 

You name a few old wizards and call it a proof? You want me to look through all their individual stuff? Be more clear, or I might as well say you should open your eyes as a proof.

 

Intel has increased the execution port number from 6 to 9, increased ALU count from 3 -> 4 in what 8 years? At some point, the hardware needs to advance for the software developers to take advantage of. We have SIMD, which are very useful for SIMD related workloads. You do realize most software use MIMD? Any multi-threaded software in fact.

 

Patrick, you clearly don't know what I'm talking about in regards to netburst. I'm not talking about introducing 2 ALUs, but rather have the ALUs run 2x the clock speed of the CPU, giving the effect of a 0.5 cycle execution for normal 1 cycle executions. Sure, to store the result the instruction latency appeared the same (to not mess up with cache subsystems), but intermediate executions was possible iirc. Ie, you could reuse the value generated in the first 0.5 cycle in the next 0.5 cycle, effectively cutting the data latency by half in relative to CPU clocks.