AMD zen based Opteron slides showcased in a debate at CERN

[patrickjp93]

5 hours ago, zMeul said:

I might be looking at this wrong, but looks like they will split the cores in packages - basically having multi CPUs on the same die

didn't Intel do a similar thing with the 1st gen Core i ?! or was it earlier in Core DUO

Core 2 Duo and Core 2 Quad were MCMs, but not Core i.

[patrickjp93]

5 hours ago, Bouzoo said:

To be fair Skylake Xeons will have 28 cores, and iirc their Xeon Phi will have 72 cores iirc. 

 

5 hours ago, dalekphalm said:

The Xeon Phi is not an Apples to Apples comparison to a Xeon or Zen CPU. The Phi is more of a hybrid between GPGPU compute cores, and a traditional CPU. AFAIK, it also takes up an entire PCIe card slot as an add-in board.

 

So while it could possibly do many of the same things as a Zen CPU, it's hard to compare them exactly.

That went out the door with Knight's Landing which has system-CPU form factors in addition to PCIe accelerators. And they are pure CPU cores. Atom cores with 2 512-bit vector units each, but CPU cores all the same.

[FPSwithaWacomTablet]

So while Intel offers hyperthreading...

 

AMD offers half-threading? I mean they're literally fusing two CPUs into one.

[dalekphalm]

54 minutes ago, FPSwithaWacomTablet said:

So while Intel offers hyperthreading...

 

AMD offers half-threading? I mean they're literally fusing two CPUs into one.

Haha!

 

/s

 

Seriously though, AMD will be offering SMT (Hyperthreading is a type of SMT), with a 1:2 ratio (same as Intel - 1 Core : 2 Threads). Intel has also used MCM before (Fusing two CPU "dies" together into one big chip), as has AMD, so even if that's the case, this is nothing new.

 

Again, I will reiterate, the MCM portion is pure speculation.

[Dabombinable]

3 minutes ago, dalekphalm said:

Haha!

 

/s

 

Seriously though, AMD will be offering SMT (Hyperthreading is a type of SMT), with a 1:2 ratio (same as Intel - 1 Core : 2 Threads). Intel has also used MCM before (Fusing two CPU "dies" together into one big chip), as has AMD, so even if that's the case, this is nothing new.

 

Again, I will reiterate, the MCM portion is pure speculation.

I don't understand even why they'd use MCM again, core scaling isn't as good when its used.

[dalekphalm]

9 minutes ago, Dabombinable said:

I don't understand even why they'd use MCM again, core scaling isn't as good when its used.

Well, that's why I don't think it'll be used.

 

The author of the article basically said "I think they'll use MCM, because the PileDriver Opteron's use MCM"... makes no sense at all.

[looncraz]

12 hours ago, Prysin said:

i wonder how that would affect their APUs though.

 

i mean, if you look at gaming loads you see massive jumps going from single to dual channel RAM. Now, server stuff is a different beast, but 8 channels sure should grant a hell of a lot of bandwidth.

 

One can't help to wonder if this is the "disruptive" bandwidth previous hinted at by AMD slides.

[Trixanity]

2 hours ago, valdyrgramr said:

Snip

What you're describing is Bulldozer and its derivatives. Zen will follow a model similar to Intel meaning "true" cores and SMT meaning double the threads per core (eg 8 cores 16 threads on a high end desktop SKU). 

[D-Dos Dan]

With 32 cores we might finally be able to leverage a 32 bit operating system, because each bit means support for one extra core doesn't it..........

[Dabombinable]

2 hours ago, valdyrgramr said:

No.

 

AMD does it in more of this sense, "Every core is its own thread!"  So, if you have 8 cores then you have 8 actual threads/cores.  Intel does this!  Okay, so we are going to do this!  We have 4 cores, so that's 4 true threads!  Now, we're going to use this thing called hyperthreading where we create logical/pseudo threads that aren't there, but are sorta there!  Basically, they double the threads/core by emulating the amount that are actually there.  Which can be problematic compared to ones that are actually there as there can be more of a congestion issue; however, that's not an issue as much as it was before.

 

Now, to make it more complicated.  A core has no true legit definition of what it is.  

 

So, here's what AMD does!  They have modules and cores while Intel counts their "modules" as their cores.   It's more of "depends on who you are asking" sorta thing.  So, AMD has 4 modules in their 8 cores with 2 small cores in each module.  While, to Intel, that would be a 4 core.  However, it's far more complicated than that as that's not entirely how it works either.

ALU only make up part of a core, they can't operate as a full processor on their own.

[Trixanity]

2 minutes ago, valdyrgramr said:

That's just what AMD is saying on paper, though.  When these companies put things on paper it's known to be quite different.  So, maybe or maybe not.  We will see.  All we know for sure is that AMD worked with ARM to fix their TDP issue.

Yes. AMD will definitely make Bulldozer 2.0 despite redesigning everything to switch to SMT... SMT is more threads per core. There is no argument about it. Now the implementation of this and performance of it is in question but that does not mean it'll be one FP unit per two cores as you claim. They have made several diagrams showing the workings of Zen. Those are not PR crap.

 

And in what way have AMD been working with ARM regarding TDP? Never heard of this and it makes little sense. Correct that they have licensed ARM v8 and have made the Seattle processor as well as having K12 on the way but it's pretty doubtful ARM would be working on x86 for another company. It's also doubtful that AMD would need that help. They have plenty engineers to do their own work on processors. The whole TDP thing is a product of inefficient design and of pushing the frequencies of a chip past its intended speed in order to be anywhere near competitive. 

 

To reiterate: very doubtful ARM has had any hand in Zen and doubtful that they had any influence on TDP. Might have send engineers to help with some elements of K12 and/or Seattle but that's a different product. 

[Ashaira]

20 hours ago, Eroda said:

nothing to stop dual socket MB running 64C/128T setup either but only time will tell

2 cpus 16 gamers machine confirmed.

[Prysin]

 

AMD worked with arm to gain TrustZone. This has been rumored to be in ZEN too. What it does is simplify hardware security between devices. They want or need nothing else from ARM. It is there to make their product A LOT more tempting to potential business partners.

As for TDP, TDP is a byproduct of voltage. Voltage is a byproduct of process node and clock speeds.any product can have low TDP by either having a very low node (10-14nm) or by having very low clock speeds (think laptop CPUs). There is no other witchcraft behind it.Why does process node matter? Because the larger the node, the more power leaks every time a transistor gate opens or closes. This means you waste energy. Instead of a true analogue 1 or 0, you end up with a peak + curve. What you want is a peak and zero curve, because that induces a lot less heat.
Smaller gates (smaller node), opens faster and closes faster. Thus less energy is wasted on switching state of the transistor (open or closed state).

The main reason Intel is much more efficent atm is because of a lower processing node. But also because of a finer voltage control. HOWEVER, Intel and AMD rates their TDP differently.
Intel rates it as "typical workload" Which means if you start rendering 24/7, Intels TDP wont be 88w, it will be higher. Probably closer to 100w or more.AMD on the other hand measures Peak power draw. So the highest power draw you would see. Which would be just as your start rendering or doing complex AVX algorithms. They are not 100% accurate in actual power draw at max power and load either, but they are much more "honest" in this sense then intel is.

So how much power does a AMD CPU draw?
My 7870k has a beefy iGPU.... which is rated at 15w peak TDP. The CPU + iGPU is rated at 95w... but how much does it really pull? Well, crude tests suggest around 45-50w under gaming load (using dGPU to take load off iGPU). So that puts AMDs product at 60-65wTDP. However if you start Folding at Home with an APU, it will occasionally spike up to 80-90w depending on the load. Therefore, AMD played it safe and rated it WAY higher then what it really does use. Or, they may just have not said anything, but people assume its 95w, because they bundle their old 95w FX cooler with the product.
AMD is really shit at explaining their stuff, or even informing users in a understandable and easy to look up way. So who knows what they really do say or not. More often then not, you are better off testing their stuff yourself then believe in what AMD says.

Anyway, i amd looking forward to this new Opteron, their current stuff isnt great, but it isnt as terrible as you'd think. But that is mostly because they cost half that of a Xeon, their boards are cheaper, and they deliver 70% of Xeon performance but uses more power. Thank god servers are well optimized, but that is thte only reason FX Opterons even was competitive at all.If you woner how FX stacked up against Xeons, go read this article here:
http://anandtech.com/show/6508/the-new-opteron-6300-finally-tested

 

 

 

 

 

 

 

 

 

 

 

 

 

[linuxfan66]

15 hours ago, dalekphalm said:

Well they are building a new architecture from the ground up - sure, they might take bits and pieces from their current arch's, but I doubt they're taking too much.

 

Besides, I'm assuming at this point that the architecture itself is probably pretty well finalized and they're just working on getting ready to tape out and get engineering samples created. If you're AMD, you REALLY don't want to rush that last part, since you want to make sure your new ZEN CPU hits the ground running when it's released - not a flop like Bulldozer or Netburst.

I would make the argument that net burst laid far better groundwork than bulldozer ever did. Bulldozer never could be made that much better due to lack of ipc for sharing a key unit between two cores

[patrickjp93]

19 hours ago, dalekphalm said:

In RAM intensive high-bandwidth applications/scenarios, going 8-channel is going to make a significant boost in performance. Though it will be pretty application specific as to whether you'd see any performance increase at all or not. In many server tasks, you probably won't see any increase at all.

It will make a huge difference in compute though.

[cesrai]

On 2/10/2016 at 10:22 AM, Prysin said:

you see massive jumps going from single to dual channel RAM

Back that claim up.

[Trixanity]

59 minutes ago, cesrai said:

Back that claim up.

http://www.anandtech.com/show/10000/who-controls-user-experience-amd-carrizo-thoroughly-tested

 

Just go through all the benchmarks and read the conclusion. 

[Prysin]

 

@cesral
1 stick /channel of DDR3 = 64bit bus
2 sticks / channels of DDR3 = 128bit bus

this is a fact. No point in arguing about this.
memory bandwidth = bus width x Memory speed
Any APU, be it Intel or AMD, is massively memory bandwidth starved. This is why AMD APUs get massive improvements from using 2400MHz RAM over 1600MHz (we are talking nearly 10 FPS difference), Intel also get a boost, but due to some cache trickery on intels side, it is less obvious at first, but the boost is there.
 

 

 

 

 

 

 

 

 

 

 

[patrickjp93]

15 hours ago, dalekphalm said:

Well, that's why I don't think it'll be used.

 

The author of the article basically said "I think they'll use MCM, because the PileDriver Opteron's use MCM"... makes no sense at all.

In all likelihood, it will be used. GloFo does not do big, monolithic dies well.

[patrickjp93]

4 minutes ago, Prysin said:

 

@cesral
1 stick /channel of DDR3 = 64bit bus
2 sticks / channels of DDR3 = 128bit bus

this is a fact. No point in arguing about this.
memory bandwidth = bus width x Memory speed
Any APU, be it Intel or AMD, is massively memory bandwidth starved. This is why AMD APUs get massive improvements from using 2400MHz RAM over 1600MHz (we are talking nearly 10 FPS difference), Intel also get a boost, but due to some cache trickery on intels side, it is less obvious at first, but the boost is there.

Cache "trickery?" Intel just has much more cache that operates at very high bandwidth, very low latency, and is attached to a highly advanced prefetcher.

[Tomsen]

2 hours ago, linuxfan66 said:

I would make the argument that net burst laid far better groundwork than bulldozer ever did. Bulldozer never could be made that much better due to lack of ipc for sharing a key unit between two cores

I would very much doubt that. Both were failures, but one is a newer and slightly more advanced failure..

The high-performance team was moved on to zen project rather quickly, and the lower-power team (previously responsible for jaguar-line) took over after piledriver.

Hence why steamroller and excavator was more efficiency / performance focused, rather actually having higher performance than its predessor.

 

31 minutes ago, patrickjp93 said:

Cache "trickery?" Intel just has much more cache that operates at very high bandwidth, very low latency, and is attached to a highly advanced prefetcher.

Cache trickery, secret sauce or whatever one would like to call it.

The secret sauce is how you get the cache to operate at very high bandwidth and very low latency.

[MageTank]

On 2/10/2016 at 9:22 AM, patrickjp93 said:

8-channel DDR4? Interesting.

Interesting good? or Interesting bad? Because i have a bad feeling that its IMC is going to be extremely weak if its "8 channels". Makes me believe they are going to use channel switching, rather than point to point, which means Xeon's will still likely eat this Opteron alive.  Not to mention this thing is launching against Purely, and if it lacks AVX512, then there is even more concern.  

[Tomsen]

7 minutes ago, MageTank said:

Interesting good? or Interesting bad? Because i have a bad feeling that its IMC is going to be extremely weak if its "8 channels". Makes me believe they are going to use channel switching, rather than point to point, which means Xeon's will still likely eat this Opteron alive.  Not to mention this thing is launching against Purely, and if it lacks AVX512, then there is even more concern.  

That will depend on how their building block is looking. I'm thinking 2 modules (8 cores) + 2 MC. Gives great modularity for scaling up or down in channels.

Doubt AVX512 is going to be a great concern, perhaps for few certain areas. Those areas can be filled up with HSA APUs.

[patrickjp93]

38 minutes ago, Tomsen said:

That will depend on how their building block is looking. I'm thinking 2 modules (8 cores) + 2 MC. Gives great modularity for scaling up or down in channels.

Doubt AVX512 is going to be a great concern, perhaps for few certain areas. Those areas can be filled up with HSA APUs.

AVX 512 means double the compute per clock, not to mention Intel's bringing the Cannonlake graphics engine to its Skylake E5 and E7 Xeons.

[dalekphalm]

7 hours ago, D-Dos Dan said:

With 32 cores we might finally be able to leverage a 32 bit operating system, because each bit means support for one extra core doesn't it..........

32-bit architecture and core count really don't have much to do with each other...

 

Not to mention, we've been on 64-bit Operating Systems for what... 10 years? Windows XP x64 Edition was released just under 11 years ago.

 

The "bit" refers to memory addressing. The main benefit of going 64-bit is that you can address much higher amounts of physical memory.