Intel's Skylake CPUs for PCs won't support AVX-512 a.k.a. AVX3

[zMeul]

source: http://www.bitsandchips.it/hardware/9-hardware/5294-avx-512-solo-per-gli-xeon-skylake-e-non-i-core-skylake%20 via KitGuru
 

Support of 512-bit SIMD instructions – known as AVX3 – was expected to be a key feature of Intel “Skylake” processors, which would help the chips to demonstrate extremely high performance in applications that take advantage of the innovation. However, Intel decided not to enable any AVX-512 instructions in consumer versions of the code-named “Skylake” processors, reports Bits & Chips web-site. While future Xeon chips that belong to the “Skylake” generation will support select AVX-512 instructions. Apparently, even Xeon processors featuring the new cores will not support certain 512-bit instructions supported by Xeon Phi “Knights Landing” co-processors.

 

As it turns out, only “Cannonlake” processors due in late 2016 or early 2017 will support most AVX-512 instructions, but not all of them. It is also unclear whether consumer versions of “Cannonlake” CPUs will have comprehensive support of 512-bit instructions.

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that's a bummer; this is what happens when you don't have competition on desktop (workstation) sector
 
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Intel® Advanced Vector Extensions 512 (Intel® AVX-512)
In the future, some new products will feature a significant leap to 512-bit SIMD support. Programs can pack eight double precision and sixteen single precision floating numbers within the 512-bit vectors, as well as eight 64-bit and sixteen 32-bit integers. This enables processing of twice the number of data elements that IntelAVX/AVX2 can process with a single instruction and four times the capabilities of Intel SSE.
 
Intel AVX-512 instructions are important because they open up higher performance capabilities for the most demanding computational tasks. Intel AVX-512 instructions offer the highest degree of compiler support by including an unprecedented level of richness in the design of the instruction capabilities.
 
Intel AVX-512 features include 32 vector registers each 512-bit wide and eight dedicated mask registers. Intel AVX-512 is a flexible instruction set that includes support for broadcast, embedded masking to enable predication, embedded floating point rounding control, embedded floating-point fault suppression, scatter instructions, high speed math instructions, and compact representation of large displacement values.

[Brainless906]

Don't worry, we'll totally have competition...in like...2016...sigh

 

AMD sat on thar hands far to long and the consumer ends up paying.

[Watsyurdeal]

Not to sound stupid but what is AVX3?

Does it actually mean anything important to me or is it just one of those things I'll likely never use or notice?

[zMeul]

Don't worry, we'll totally have competition...in like...2016...sigh

 

AMD sat on thar hands far to long and the consumer ends up paying.

no, I actually don't believe can close the gap with their new lineup - AMD is still (and will continue) plays catch-up for quite a very long time now

 

this is AMD:

 

kicking the can while intel has a nice cold drink at the beach

[vm'N]

Not to sound stupid but what is AVX3?

Does it actually mean anything important to me or is it just one of those things I'll likely never use or notice?

AVX3 or AVX-512 is Intels upcomming AVX extention. Increase the width of the previous AVX extention (AVX2 or AVX-256) and introduce some better gather-scatter instructions IIRC.

 

If it means anything to you? No, not all all.

[Ostwind]

AVX3 or AVX-512 is Intels upcomming AVX extention. Increase the width of the previous AVX extention (AVX2 or AVX-256) and introduce some better gather-scatter instructions IIRC.

 

If it means anything to you? No, not all all.

Try again, this time in english

[zMeul]

Try again, this time in english

to dumb it down to extremes, AVX is very good for video editing, an example

[vm'N]

Try again, this time in english

Okay. When your processor is doing a ton of work, and there will be a workload, like adding +18 to x amount of data-elements. Instead of going over it serialized (one after another), you load all the elements into your SIMD cluster, which then will do a single operation to all the data-elements in parallel.

 

Increased width means you can have more data-elements.

Gather-scatter is used to simplify the loading / storing of the elements for vector code.

[zMeul]

Okay. When your processor is doing a ton of work, and there will be a workload, like adding +18 to x amount of data-elements. Instead of going over it serialized (one after another), you load all the elements into your SIMD cluster, which then will do a single operation to all the data-elements in parallel.

 

Increased width means you can have more data-elements.

Gather-scatter is used to simplify the loading / storing of the elements for vector code.

I'm sure he's like .. 

 

[DEDRICK]

Okay. When your processor is doing a ton of work, and there will be a workload, like adding +18 to x amount of data-elements. Instead of going over it serialized (one after another), you load all the elements into your SIMD cluster, which then will do a single operation to all the data-elements in parallel.

 

Increased width means you can have more data-elements.

Gather-scatter is used to simplify the loading / storing of the elements for vector code.

 

So basically it's magic

[patrickjp93]

So basically it's magic

If software developers are smart and use good coding practices and allow compilers to do optimization, you get SIMD code, or 1 instruction affecting multiple data, such as add/sub/mul/div two vectors, or doing logical and/or/xor across multiple data elements. The more SIMD you have, the fewer instructions you need, and the faster you run (in general. There are exceptions). AVX 512 doubles the number of data items you could process simultaneously, or theoretically doubling your potential performance, but your code needs to be written well enough for a compiler to see its usage as possible and optimal. While refactoring a code base for AVX 256 is not difficult (8x32 or 4x64), 512 is very tough (16x32, 8x64) and compilers are only just beginning to experiment with it. No one uses enough doubles in general code to shorten the number requirements, though GCC, Clang, and ICC are all getting better at inter-function optimization through in-lining code and letting functions run in parallel at the instruction level instead of requiring it happen at the thread level.

 

In Java/C# it will be years before you see a JIT environment make any use of this. For some of the native implementations, it could be sooner, but there's a reason C/C++ are still regarded as the highest performance languages in the world. Simply put, the best minds in the world work on the compilers,  and the other best minds work on the language standards. Google's GO may be easier to write in and get parallel implementations (though, seriously, if you use C++ without OpenMP for at least some of your multithreaded work, you're kind of doing it wrong at this point, or you're the kind of nut who can optimize further at the assembly level by using C/C++ native threads), it still lags in performance in a lot of areas. We'll see how far Google can take it.

[Sintezza]

We allready see a huge improvement in rendering times, with application that use AVX2 instructions.

If skylake doesnt use AVX3 that would indeed be a bummer, however only a few applications are slowly starting to use avx2.

So i dont think it would be a realy big deal for skylake.

[patrickjp93]

We allready see a huge improvement in rendering times, with application that use AVX2 instructions.

If skylake doesnt use AVX3 that would indeed be a bummer, however only a few applications are slowly starting to use avx2.

So i dont think it would be a realy big deal for skylake.

And you could always get an E3 Xeon that doesn't cost much more than the I7s anyway to get AVX 512.

[Sintezza]

And you could always get an E3 Xeon that doesn't cost much more than the I7s anyway to get AVX 512.

 

well 1 thing that botters me more, is that unlocked skylake chips might not fully support all virtualization instructions anymore.

Atleast according to some "rumors" it looks like that there are going to be a split again just like sandy and ivybridge days.

Most likely we are going to see Z and Q series boards, which gives me the bad feeling that unlocked i7's could maybe not support vt-d and such.

 

Thats would be a bigger bummer to me. :unsure:

[zMeul]

And you could always get an E3 Xeon that doesn't cost much more than the I7s anyway to get AVX 512.

not even Xeons will have support for all the AXV3 instructions

[Berkut99]

I had thought there was already mention of the fact that Skylake was forgoing on AVX-512 months ago. http://wccftech.com/mainstream-intel-core-processors-support-avx-512-skylake-xeon/

 

Although it is WCCFTech, so... I suppose filing that in the ignore bin was probably justified.

 

But between the issues that Intel had making it to 14nm and their decision to make unexpected changes to Skylake like needing to move the FIVR off the chip, I don't think this has anything to do with Intel being lazy because of lack of competition; I think this is Intel running into problems at the manufacturing level.

[vm'N]

not even Xeons will have support for all the AXV3 instructions

Some of them are designed for/around the KL. Xeons should support all the "regular" AVX instructions.

[patrickjp93]

not even Xeons will have support for all the AXV3 instructions

True, but that was true of AVX 2 as well. Every extension set gets tweaks over the years. And the ones not supported in Skylake are a fair bit more exotic and are best suited to aiding encryption instructions.

[patrickjp93]

I had thought there was already mention of the fact that Skylake was forgoing on AVX-512 months ago. http://wccftech.com/mainstream-intel-core-processors-support-avx-512-skylake-xeon/

Although it is WCCFTech, so... I suppose filing that in the ignore bin was probably justified.

But between the issues that Intel had making it to 14nm and their decision to make unexpected changes to Skylake like needing to move the FIVR off the chip, I don't think this has anything to do with Intel being lazy because of lack of competition; I think this is Intel running into problems at the manufacturing level.

FIVR was a testing/proving ground for its SOC development. I don't think anyone expected it to stay due to the extra heat it added to the package when overclocking. Perhaps it lowered motherboard prices and allowed better use of board space, but it was adding problems elsewhere. I don't think Intel's really having any manufacturing/production problems beyond the fact we're getting into quantum tunneling territory soon and parasitic capacitance is a real issue now. We'll see what the future holds.

[Ostwind]

Okay. When your processor is doing a ton of work, and there will be a workload, like adding +18 to x amount of data-elements. Instead of going over it serialized (one after another), you load all the elements into your SIMD cluster, which then will do a single operation to all the data-elements in parallel.

 

Increased width means you can have more data-elements.

Gather-scatter is used to simplify the loading / storing of the elements for vector code.

to dumb it down to extremes, AVX is very good for video editing, an example

[PlayModeOn]

How does this effect gaming?

[MegaDave91]

How does this effect gaming?

 

This lack of instruction set is in no way detrimental to those who don't require it. If you didn't know Skylake wasn't going to feature this; you wouldn't know it's non-existent.

[patrickjp93]

How does this effect gaming?

Most games still don't take advantage of SSE and AVX 1. EVENTUALLY it'll matter, but by that time we'll have even more instructions on even newer hardware.

[deviant88]

Not to sound stupid but what is AVX3?

Does it actually mean anything important to me or is it just one of those things I'll likely never use or notice?

Nope 100% worthless,unles you are programmer/work/scientific/server stuff with number crunching this is useless for most apps like your media player or games.

Who knows if windows kernel and Directx might take a small advantage in day to day computing.

And no i dont know what i am talking about, i read enought about AVX and the only AVX game was GRID forgot which version showed 0% improvement with AVX intructions benchmark, so avx3 its even less useful for 99% of what we do on home pc's.

[LukaP]

Most games still don't take advantage of SSE and AVX 1. EVENTUALLY it'll matter, but by that time we'll have even more instructions on even newer hardware.

They are using SSE3 if they are on Unreal 4+ or Unity 4+ and run on compatible hardware (basically everything made after 2004), but yeah, it would be beneficial to include an AVX compiled version of the engines for those wishing to use it.

 

On the subject of AVX512, my thoughts of upgrading have once again been moved. Skylake-EP it is. (or Zen if its competitive)