Do AMD chipsets still have an MCH (northbridge)?

[Speedbird]

Hi.

So I bought an ASRock 960GM-VGS3 FX board about a week ago which uses the 760G chipset. This gave me a question: Does AMD still use the northbridge? I noticed that the 760G has one and I'm wondering why haven't they moved to IMCs and PCHs. That board was AM3+ but I'm also asking about FM2 and FM2+.

[Aniallation]

Hi.

So I bought an ASRock 960GM-VGS3 FX board about a week ago which uses the 760G chipset. This gave me a question: Does AMD still use the northbridge? I noticed that the 760G has one and I'm wondering why haven't they moved to IMCs and PCHs. That board was AM3+ but I'm also asking about FM2 and FM2+.

AM3 uses a northbridge, however the IMC is built into the CPU (which is why AM3 CPUs can support DDR2 or DDR3, and they can work in AM2+ motherboards). The APU platforms don't. They've moved things onto the chip itself now.

[Speedbird]

AM3 uses a northbridge, however the IMC is built into the CPU (which is why AM3 CPUs can support DDR2 or DDR3, and they can work in AM2+ motherboards). The APU platforms don't. They've moved things onto the chip itself now.

I believe that the northbridge performs the same functions as an IMC. So why are there both?

[Aniallation]

I believe that the northbridge performs the same functions as an IMC. So why are there both?

 

Cause from 462 to AM3 design the NB runs the PCIe controller and connects to the SB, which does things like USB, SATA, etc. This is why HyperTransport exists, because these things aren't directly interfacing with the CPU like they are with Intel, it still keeps latency to a minimum. 

 

Also, on some boards the NB also contains the crappy integrated graphics, since that's not built into the CPU either.

[Speedbird]

Cause from 462 to AM3 design the NB runs the PCIe controller and connects to the SB, which does things like USB, SATA, etc. This is why HyperTransport exists, because these things aren't directly interfacing with the CPU like they are with Intel, it still keeps latency to a minimum. 

 

Also, on some boards the NB also contains the crappy integrated graphics, since that's not built into the CPU either.

Oh, okay. So HyperTransport is like the DMI/FSB?

[Faa]

Oh, okay. So HyperTransport is like the DMI/FSB?

No. FSB is between the cpu and the northbridge=memory/pcie controller. Hypertransport is between the cpu and pcie controller/southbridge excluding the memory controller because the IMC has her own bus called the memory bus. FSB was replaced by QPI and QPI is gone with Sandy bridge since they moved the pcie controller and the memory controller was already in the cpu with nehalem if I'm not mistaken so they decided to have them in a loop aka the ring bus (bclk). DMI is just the link between the nb & sb, kaveri uses UMI to do this instead of HT.

Picture for HT: http://www.hardwaresecrets.com/fullimage.php?image=3929

FX series still have the mem/pcie controllers in the northbridge die, lliano moved the gpu (was located in the nb die communicating through HT before) along with the mem/pcie controller to the cpu die but they are still separated. So whats the definition of "no northbridge anymore"? Having the chipset in the cpu die? Then sandybridge+ and lliano APU's+ don't have it a NB anymore. Their new APU's got rid of HT and use UMI instead to connect the SB with the cpu

 

[-rascal-]

@Faa pretty much got it all there.

 

Just to add:

As far as I know, the IMC has been in the CPU since at least socket AM3. On AMD CPU's there a part called the "CPU-NB" which connects the CPU to the IMC.

Aside from that, there is still NB and SB on socket AM3+, but things have started to migrate with the newer APU's. Heck they started back with socket FM1 (first generation APU's).