Via are back with new x86 CPU architecture

[porina]

Quote

CHA is Centaur’s new data center and edge server SoC. But it’s not your usual edge server SoC. We think Centaur has something really special here. It’s a new ground-up design that features eight high-performance x86 cores along with a new clean-sheet design AI coprocessor. The inference market is just starting to explode and what’s better than a processor connected to a powerful AI accelerator card? One that comes with one deeply integrated, of course. What Centaur came up with is a pretty powerful accelerator. For completeness, we want to note the individual core microarchitecture is codenamed CNS while the AI coprocessor codename is NCORE.

 

Source: https://fuse.wikichip.org/news/3099/centaur-unveils-its-new-server-class-x86-core-cns-adds-avx-512/

 

CHA is the codename for the chip (e.g. comparable to Matisse, Coffee Lake) and we don't know what the marketing name for actual product is yet, since this is an architecture reveal, not a product announcement. Centaur are owned by Via.

 

We see 8 cores with something resembling a ring bus. Quad channel ram should feed that well. The AI copro branches off, as does an interchip link and southbridge including 44 PCIe 3.0 lanes. I recommend clicking through if you want the details on the architecture, but the tldr take away point is that the x86 part of the architecture is competitive to current Intel and AMD designs. They built it ground up, in a way that might be compared to how AMD bought us Ryzen.

 

So what does this offer compared to Intel and AMD? Note this is targeted at server space, so before you declare it dead against Zen 2 offerings, consider where it is aimed at. This is the first architecture to offer AVX-512 support outside of Intel, although it is only equivalent to a one-unit AVX-512 implementation so wont see the speedups like that of Skylake-X and newer for FP64 heavy use cases. The NCORE AI copro is interesting, and will no doubt form a key part of its reason for existing. This isn't my special interest area, but Intel have VNNI as part of later AVX-512 extensions, so presumably they're going for the same market. As far as I'm aware, AMD have nothing in this area. Someone buying this is not the same person buying Epyc.

 

Still, it is interesting to see a new design appear in the x86 area. Presuming they're targeting server applications as a profitable area first, if it goes well I wonder if there is room for them to offer cut down versions in the prosumer space.

 

Edit 15 Dec: I missed it 1st time but the linked article claims this will be made on TSMC 16nm.

[Princess Luna]

In before Can it run Crysis...

 

That's nice, lets all welcome VIA back to the market and hope they succeed for the best competition has to offer.

[porina]

Just now, Princess Luna said:

In before Can it run Crysis...

8 cores aren't bad (for gaming) but we don't know anything about clocks. Or process node. 

[Brooksie359]

Looks like there will be three players in the GPU and CPU markets. 

[Bcat00]

At this point i dont even care who comes in, just more coming in is a sight to behold in this day and age

[amdorintel]

1 hour ago, porina said:

8 cores aren't bad (for gaming) but we don't know anything about clocks. Or process node. 

you saying then 12 cores for gaming is best?

[S w a t s o n]

I heard about this but didnt realize they were owned by VIA. Many x86 patents are expiring soon and I assumed they leveraged those.

[mr moose]

If VIA don't call it the C9 on launch I will be sorely unimpressed. 

 

 

[justpoet]

Should be interesting.  I look forward to it shipping and seeing how it turns out.  The concept is good, so let's see how the implementation works out.

[RejZoR]

I remember when we were selling laptops with VIA CPU's powered by Chrome GPU. That was back in around 2008 iirc. Would be nice if VIA returned with CPU's and GPU's. Just imagine future where we have 3 CPU makers and 4 GPU makers? That would be like 90's revisited

[Master Disaster]

4 hours ago, porina said:

8 cores aren't bad (for gaming) but we don't know anything about clocks. Or process node. 

Or IPC...

[pas008]

6 hours ago, porina said:

8 cores aren't bad (for gaming) but we don't know anything about clocks. Or process node. 

 

1 hour ago, Master Disaster said:

Or IPC...

Considering everything going 4k gaming wise might not be as a big deal depending on price ofc

I know this is server class but....

 

[Taf the Ghost]

19 minutes ago, VegetableStu said:

oh hey, just in time for x86's patents to expire o_o

 

now to assign a colour to VIA

I think they were White back in the day? Cyrix was Green, but they're gone.

 

As for the x86 patents, those actually expired a long time ago. It's the SSE2 patents that are up in 2020, it seems. Also seems like the AMD64 patents are as well, but VIA is strange because they actually have a true x86 license from Intel, so the only real hang up would be a cross-license with AMD. That might be part of the reason this isn't launching yet, as they need 64-bit address space patents to roll off.

[Taf the Ghost]

Just now, VegetableStu said:

oh mmm. was lacking this part of info o_o

The x86 patent fall off got to be something of at talking about a few weeks ago, but I've yet to track down which patents. Generally you have 14 years on a US-based patent, but some are long (20 or 21) so I'm not exactly sure which patents everyone is talking about. So it's either patents falling off from 1999 or 2006. 1999 would be SSE2 and x86-64.

 

However, https://en.wikipedia.org/wiki/VIA_Nano exists and VIA already had x86-64 rights. So that isn't a reason involved with VIA. It could matter to others, though.

[porina]

28 minutes ago, Tedny said:

Bulldozer with split l3 cash? 

I'm not familiar with Bulldozer but in a quick look, that appears to have blocks of L3 cache per module which is shared between all modules. I don't know if there is any latency variation depending on which block of L3 it is in.

 

The Centaur design reminds me of Intel ring bus. A portion of L3 is associated with a core, and all L3 remains accessible by all cores via the ring bus. Think the downside to this approach is that latency to L3 data varies depending on how many hops around the ring you have to go to get it, so it works better at lower core counts.

 

Current Zen (up to Zen 2) approach is L3 is only shared within a CCX. If you want data not in the local CCX, you have to go back to ram to get it, even if it is on the other CCX on die there is no way to access it. This partitioned approach limits the benefit of L3 cache size, but may have benefits in latency/bandwidth for stuff within CCX. It is a tradeoff made during design. Zen 3 is supposed to get rid of this barrier so that a CCD has a single block of L3 which for my uses will help a lot.

[Doobeedoo]

Ooh well cool to see. 

[ravenshrike]

By the time this is actually out won't AMD be on Zen 3? Or are they launching 1st or 2nd quarter of next year?

[porina]

29 minutes ago, ravenshrike said:

By the time this is actually out won't AMD be on Zen 3? Or are they launching 1st or 2nd quarter of next year?

Don't think any product has been announced yet.

 

Unless Zen 3 has AI "stuff" added to it, it wont be competing in the same area anyway. Look again at the feature set. They're not blindly throwing cores at things, but the selling point is probably going to be the AI copro. 

[leadeater]

4 minutes ago, porina said:

Don't think any product has been announced yet.

 

Unless Zen 3 has AI "stuff" added to it, it wont be competing in the same area anyway. Look again at the feature set. They're not blindly throwing cores at things, but the selling point is probably going to be the AI copro. 

Willing to bet 40%-60% of the die is going to be the NCORE.