Ryzen 5 3600 idle voltage is 1.4 - 1.45 always

[leonid1019]

1 minute ago, Taf the Ghost said:

HWmonitor is busted. The information you've gotten from it is worthless for dealing with Zen2. That's why I said you use something else so far back in the thread.

CPU-Z. Ryzen masters show the same results

[SavageNeo]

1 minute ago, leonid1019 said:

CPU-Z. Ryzen masters show the same results

What exact model of ram you have. Show me screen shot, use windows photocapture program

[Taf the Ghost]

1 minute ago, Columbo said:

AMD pumps a lot of voltage into stock 3600 processors because the silicon is not the best binned chips. Manually reducing the Vcore until you hit a level where you do not get blue screens, soft crashes or application instability. 

No. That's completely wrong. Zen2 uses on-silicon voltage regulation to allow much faster boost & frequency shifts. (Intel does this, as well.) The 1.4V reading is doing nothing because the cores are actually parked. If the core goes under sustained load, the reported voltage drops to the actual voltage being used, as they normalize out because of the current draw.

 

Basically, AMD shouldn't have let us see the clever electrical engineering they did because it confused people.

[leonid1019]

2 minutes ago, SavageNeo said:

What exact model of ram you have. Show me screen shot, use windows photocapture program

You mean this?

[SavageNeo]

Just now, leonid1019 said:

You mean this?

go to SPD next of the memory and screen shot form there. WTF 2400mhz memory cl 16, that very bad for ryzen third gen. Like the sweet spot is 3600mhz cl16

[Columbo]

7 minutes ago, Taf the Ghost said:

No. That's completely wrong. Zen2 uses on-silicon voltage regulation to allow much faster boost & frequency shifts. (Intel does this, as well.) The 1.4V reading is doing nothing because the cores are actually parked. If the core goes under sustained load, the reported voltage drops to the actual voltage being used, as they normalize out because of the current draw.

 

Basically, AMD shouldn't have let us see the clever electrical engineering they did because it confused people.

 

4 minutes ago, SavageNeo said:

go to SPD next of the memory and screen shot form there. WTF 2400mhz memory cl 16, that very bad for ryzen third gen. Like the sweet spot is 3600mhz cl16

Here is shit Hynix memory timings. That is DDR4 3200mhz

[SavageNeo]

Just now, Columbo said:

 

Here is shit Hynix memory timings. That is DDR4 3200mhz

mine are not that good either, but better than that guys 2400mhz. 

 And btw since you are lower than me (3200mhz) why the earth your bank cycle time is so big? do u use ryzen master for that memory?

[Columbo]

2 minutes ago, SavageNeo said:

 And btw since you are lower than me (3200mhz) why the earth your bank cycle time is so big? do u use ryzen master for that memory?

Why is your FSB:GRAM ratio not 1:1?

[leonid1019]

3 minutes ago, Columbo said:

Why is your FSB:GRAM ratio not 1:1?

if i knew what that means at all... Is it bad?

[leonid1019]

5 minutes ago, Columbo said:

Why is your FSB:GRAM ratio not 1:1?

Now it is 1:12

[Columbo]

I updated my bios to Agesa 1.0.0.4 

I have updated my memory timings. 

[SavageNeo]

7 minutes ago, Columbo said:

Why is your FSB:GRAM ratio not 1:1?

The FSB is QDR, or Quad-Data-Rate. It transfers data four times per cycle, so a 200Mhz FSB results in 800 MT/s across the Front Side Bus.

DDR SDRAM is DDR, or Double-Data-Rate. It transfers data two times per cycle, so a 400Mhz DDR-SDRAM results in 800 MT/s across the DRAM IO Bus (a channel).

DDR3-1600 necessarily has an 800Mhz clock. This is derived from the FSB using the FSBRAM ratio. A 1:4 ratio means that the DRAM clock is 4x faster than the FSB clock. This clock multiplication is accomplished using a PLL, or Phase-Locked-Loop.

A source clock signal is fed into the PLL, and one or more derived clocks can be generated. One of the clocks outputs will be the source clock that was fed in, and all other clocks outputs may be some multiple of this source clock. The PLL can both multiply and divide the clock (which allows for fractional ratios such as 2:3 which multiplies by 3 and divides by 2 to yield 1.5) as well as adjust the phase of derived clocks relative to the source clock.

In most motherboards, an oscillator (either a crystal oscillator, or a voltage controlled oscillator) is used to drive a Schmitt trigger, which in turn drives a clock buffer, and the output of this clock buffer is used as the source for the PLL. In many cases, this is all integrated into one chip.
 

[SavageNeo]

Just now, Columbo said:

I updated my bios to Agesa 1.0.0.4 

I have updated my memory timings. 

nice!

[Columbo]

2 minutes ago, leonid1019 said:

Now it is 1:12

Your memory divider is fine. 1:12 1:16 is still 1:1 divider. But that other guy is 3:5

[SavageNeo]

3 minutes ago, leonid1019 said:

Now it is 1:12

what did you do? do not change anything if you do not know how?

[leonid1019]

20 minutes ago, SavageNeo said:

what did you do? do not change anything if you do not know how?

I didn`t change anything, it changes automaticly

[leonid1019]

Anyway, my processor is still running at 1.4v. And I can’t understand if this is normal.

[SavageNeo]

Just now, leonid1019 said:

Anyway, my processor is still running at 1.4v. And I can’t understand if this is normal.

Did you do what i told ya. Its normal but it should not be normal

 

[SavageNeo]

Thats my 1minute guide hot to change speed and voltage

[leonid1019]

 

 

1 hour ago, SavageNeo said:

Thats my 1minute guide hot to change speed and voltage

I`ve set pick core voltage to 1.325. 

 

[leonid1019]

Now it is 1.325 at idle

 

[Gottboost]

is it bad to set the voltage in the bios to 1.25v?