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Ryzen 3000 „Valhalla“

Nicnac

Name for the new lineup confirmed:

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The recent firmware updates have been dissected to reveal the internal codename of the Ryzen 3000 family which is internally titled as Valhalla.

This stems from an article from Wccftech

 

I like the Name, i really do ^^

....queue „see you in Valhalla“

 

also some mobos have been updated for support:

Quote

So it’s good news that motherboard manufacturers have a BIOS support this early which means that Ryzen 3000 would have pretty solid compatibility on older X370 and X470 motherboards at launch. There would also be the X570 motherboards with an improved feature set for the Ryzen 3000 series CPUs but those who don’t want to get in the hassle of upgrading their motherboards can just swap their older CPUs with the new ones and call it a day.

 

Everything looking good so far :) 

 

sorry for shitty news format today, am on mobile

 

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Vigilo Confido

 

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1 minute ago, Nicnac said:

Ryzen 3000 series CPUs

93D63CA4-FFAC-4B0A-AEF1-49095A7B8B48.jpeg.96d78a5240fc2bed9eddbcf8413e8231.jpeg

CPU: Intel Core i7-950 Motherboard: Gigabyte GA-X58A-UD3R CPU Cooler: NZXT HAVIK 140 RAM: Corsair Dominator DDR3-1600 (1x2GB), Crucial DDR3-1600 (2x4GB), Crucial Ballistix Sport DDR3-1600 (1x4GB) GPU: ASUS GeForce GTX 770 DirectCU II 2GB SSD: Samsung 860 EVO 2.5" 1TB HDDs: WD Green 3.5" 1TB, WD Blue 3.5" 1TB PSU: Corsair AX860i & CableMod ModFlex Cables Case: Fractal Design Meshify C TG (White) Fans: 2x Dynamic X2 GP-12 Monitors: LG 24GL600F, Samsung S24D390 Keyboard: Logitech G710+ Mouse: Logitech G502 Proteus Spectrum Mouse Pad: Steelseries QcK Audio: Bose SoundSport In-Ear Headphones

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A little bit old news at this point :V 
 

 

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Ex-build:

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Ryzen 5 1600x @4.0 GHz/1.4V – sold

Gigabyte X370 Aorus Gaming K7 – sold

Corsair Vengeance LPX 2x8 GB @3200 Mhz – sold

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Ah my bad

2 minutes ago, Quadriplegic said:

A little bit old news at this point :V 
 

 

havent been here in a long time ^^

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Vigilo Confido

 

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Deliverence

Why've you ever forgotten me?

 

If its "all thats promised" - a nice reference, even if unwitted

I wish Lisa would present ryzen 3000 with ride of the valkyries as a soundtrack... to bad some people are still butthurt that over alot of a time ago some bad people had good music taste.

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Valhalla is the core name. Zen1's was Zeppelin. And, yes, @VegetableStu has the correct reference for the likely naming. :)

 

The bit to come out was analysis for new features within the BIOS for Zen2 parts.

 

https://www.overclock.net/forum/13-amd-general/1640919-new-dram-calculator-ryzena-1-4-1-overclocking-dram-am4-414.html

 

 @leadeater might also find that interesting. Looking like CCXs are dead and it's now about individual chiplets. Along with some interesting stuff going on with the memory channels.

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1 minute ago, Franck said:

Any word on if B450 will support these new SKU's ?

Should. AMD is on AM4 until at least 2020. Probably 2022 at the speed DDR5 is going for adoption. Though the motherboard manufacturer is the one that has to update it.

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10 minutes ago, Taf the Ghost said:

https://www.overclock.net/forum/13-amd-general/1640919-new-dram-calculator-ryzena-1-4-1-overclocking-dram-am4-414.html

 

 @leadeater might also find that interesting. Looking like CCXs are dead and it's now about individual chiplets. Along with some interesting stuff going on with the memory channels.

Leadeater wont be the only one. For single chiplet CPUs that should make them more monolithic-like and help, but makes 2 chiplet sounds NUMA again... beyond that, I'm either misunderstanding the claims, or just need someone to draw a simple diagram of how stuff is connected. Logically I imagined an IO die going to ram and the rest, with up to two chiplets hanging off it. The concept of a chiplet having ram channels doesn't make sense to me in that context, unless the IO die is a glorified switch?

Main system: i9-7980XE, Asus X299 TUF mark 2, Noctua D15, Corsair Vengeance Pro 3200 3x 16GB 2R, RTX 3070, NZXT E850, GameMax Abyss, Samsung 980 Pro 2TB, Acer Predator XB241YU 24" 1440p 144Hz G-Sync + HP LP2475w 24" 1200p 60Hz wide gamut
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19 minutes ago, Franck said:

Any word on if B450 will support these new SKU's ?

Socket support yes, with so many cores it's more a matter of power delivery. I wouldn't go wild with the R7 3700X or R9 3800X or whatever they'll be called on B350 boards. But sticking a R5 3600X into B350 probably shouldn't be a big problem. We'll see when CPU's actually arrive tho...

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3 minutes ago, porina said:

Leadeater wont be the only one. For single chiplet CPUs that should make them more monolithic-like and help, but makes 2 chiplet sounds NUMA again... beyond that, I'm either misunderstanding the claims, or just need someone to draw a simple diagram of how stuff is connected. Logically I imagined an IO die going to ram and the rest, with up to two chiplets hanging off it. The concept of a chiplet having ram channels doesn't make sense to me in that context, unless the IO die is a glorified switch?

The channels are on the I/O die. It's just routing for topology purposes. Zen can load balance really well already, so this is probably just the result of division of memory bandwidth. There's going to be more clock domains and the ability to run the IF separate from the MemCLK. 

 

Main thing to take away is that the BIOS is setup for 16c parts. I, personally, expect those will come later in the release cycle (probably Sept/Oct) rather than at Launch. There's also a few interesting tidbits, like using the L3 of the other chiplet as a NUMA sector (i.e. L4). One implication is that we're going to see 8c, single-chiplet parts. Those will likely be the best gaming version, so it'll be interesting to see how the release cycle is effected by that.

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@porina the fixed chiplet assignment for the memory controllers is a way they handled things in Rome, almost assuredly. The 2990WX only just reached the edge of memory bandwidth issues on 4 channels and 32 cores. So, unless you're running some bandwidth bug test, I don't think it'll end up being an issue, even in most gaming contexts. Especially if the chiplet can load balance itself internally. If it's a fixed bandwidth allocation, there could be some issues when you really load up a single thread.  We'll just have to wait to see.

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Hah I though it was some meme though. At this point I really want to see that 5GHz clock with these. 

| Ryzen 7 7800X3D | AM5 B650 Aorus Elite AX | G.Skill Trident Z5 Neo RGB DDR5 32GB 6000MHz C30 | Sapphire PULSE Radeon RX 7900 XTX | Samsung 990 PRO 1TB with heatsink | Arctic Liquid Freezer II 360 | Seasonic Focus GX-850 | Lian Li Lanccool III | Mousepad: Skypad 3.0 XL / Zowie GTF-X | Mouse: Zowie S1-C | Keyboard: Corsair K63 Cherry MX red | Beyerdynamic MMX 300 (2nd Gen) | Acer XV272U | OS: Windows 11 |

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44 minutes ago, porina said:

For single chiplet CPUs that should make them more monolithic-like and help, but makes 2 chiplet sounds NUMA again...

No, its more or less the same thing as Core 2 Duo <-> Core 2 Quad.

The Memory Controller is external, though in this case its on the CPU Package and not a different one and the CPUs are connected via an Interface with the Chipset. 

 

Granted, the Core 2 was a stupid example as the FSB is shared between the two, so an AMD 760MP(X) would be a better example, but its the closest and most modern we have...

 

Quote

beyond that, I'm either misunderstanding the claims, or just need someone to draw a simple diagram of how stuff is connected.

 

IO - CPU

 

IO -> CPU

|......./

CPU

 

 

Something like that.

Gotta love ASCII Art ?

 

Quote

Logically I imagined an IO die going to ram and the rest, with up to two chiplets hanging off it. The concept of a chiplet having ram channels doesn't make sense to me in that context, unless the IO die is a glorified switch?

You have to think backwards.

 

With AMD K8 the Memory Controller went into the CPU.
With Zen2 the Memory Controller was thrown out of the CPU.


So we're basically at the same situation as before K8 and Core i.

Meaning:

 

The I/O Die is what was once the Nothrbridge.

The CPU die is what was the CPU then

The "Chipset" is what was the Southbridge.

 

So its somehting like this:

https://www.anandtech.com/show/862/2

Just that the CPUs are probably also connected with each other.

 

 

Just look at that. And think that one AMD Athlon MP Processor is a Chiplet. The 266MHz FSB is the Infinity Fabric

The AMD-762 Notrhbridge is the I/O Die.

And PCI is PCIe.

 

And you basically have a rough idea of what's going on inside the Chip.

 

 

And that Analogy also works:

https://www.vogons.org/viewtopic.php?f=25&amp;t=48043

 

All that's on the CPU Card got integrated into an AM4 Chip (minus the Voltage Regulators and Capacitors).


Its Chipset, 1 or 2 CPU Dies.

"Hell is full of good meanings, but Heaven is full of good works"

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My board is ready....

 

I just flashed it with the BIOS

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25 minutes ago, Master Disaster said:

My board is ready....

 

I just flashed it with the BIOS

I've gotta applaud that one.

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Someone at AMD's naming department really must have watched Mad Max many times...

 

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1 hour ago, Taf the Ghost said:

@porina the fixed chiplet assignment for the memory controllers is a way they handled things in Rome, almost assuredly.

If we're doing ASCII art, let me try...

 

Chiplet1---\     /-MC1---DIMM

                   IO

Chiplet2---/     \-MC2---DIMM

 

A chiplet can have a preferred memory controller, but logically to me they still hang off the IO die. Right?

1 hour ago, Taf the Ghost said:

The 2990WX only just reached the edge of memory bandwidth issues on 4 channels and 32 cores. So, unless you're running some bandwidth bug test, I don't think it'll end up being an issue, even in most gaming contexts. Especially if the chiplet can load balance itself internally. If it's a fixed bandwidth allocation, there could be some issues when you really load up a single thread.  We'll just have to wait to see.

For my workloads it is already trivially easy to saturate ram bandwidth on Intel quad cores. Zen(+) hasn't had as much problem as it is much slower but Zen2 will put it roughly on parity with non-AVX-512 Intel. My only hopes for this not to be ludicrously limited is if the aggregate L3+ cache quantity is sufficient to effectively negate the need for ram access. 32MB should be sufficient for my foreseeable needs in that respect, and attainable at 2MB/core with the big caution that bandwidth between chiplets will be a major concern. If I had to treat them as two groups for performance that would limit its use. Has the cache of Rome been officially stated? I don't recall a value for that, and can't find it in a quick search.

 

To be clear, apart from one Xeon I have, none of my Intel CPUs have enough L3 either. Oh, I have some Broadwells with L4 that work great too. I'm kinda hoping the core counts of Zen2 will enable a new level of performance that I can only dream of right now.

Main system: i9-7980XE, Asus X299 TUF mark 2, Noctua D15, Corsair Vengeance Pro 3200 3x 16GB 2R, RTX 3070, NZXT E850, GameMax Abyss, Samsung 980 Pro 2TB, Acer Predator XB241YU 24" 1440p 144Hz G-Sync + HP LP2475w 24" 1200p 60Hz wide gamut
Gaming laptop: Lenovo Legion 5, 5800H, RTX 3070, Kingston DDR4 3200C22 2x16GB 2Rx8, Kingston Fury Renegade 1TB + Crucial P1 1TB SSD, 165 Hz IPS 1080p G-Sync Compatible

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Are they trying to tell us something? Valahalla, meaning "house of the slain", ( and Freyja's field Fólkvangr) is supposed to be the place people go when they died in battle. Are they saying this is it, that this is their Valahalla? Kind of a bad code name when you look further into it. Its the same way with Navi lol.

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12 minutes ago, Dylanc1500 said:

Are they trying to tell us something? Valahalla, meaning "house of the slain", ( and Freyja's field Fólkvangr) is supposed to be the place people go when they died in battle. Are they saying this is it, that this is their Valahalla? Kind of a bad code name when you look further into it. Its the same way with Navi lol.

It's where intel is going

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4 hours ago, valdyrgramr said:

Blind Guardian wore it better.

Blind Guardian did everything better.

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53 minutes ago, porina said:

If we're doing ASCII art, let me try...

 

Chiplet1---\     /-MC1---DIMM

                   IO

Chiplet2---/     \-MC2---DIMM

 

A chiplet can have a preferred memory controller, but logically to me they still hang off the IO die. Right?

For my workloads it is already trivially easy to saturate ram bandwidth on Intel quad cores. Zen(+) hasn't had as much problem as it is much slower but Zen2 will put it roughly on parity with non-AVX-512 Intel. My only hopes for this not to be ludicrously limited is if the aggregate L3+ cache quantity is sufficient to effectively negate the need for ram access. 32MB should be sufficient for my foreseeable needs in that respect, and attainable at 2MB/core with the big caution that bandwidth between chiplets will be a major concern. If I had to treat them as two groups for performance that would limit its use. Has the cache of Rome been officially stated? I don't recall a value for that, and can't find it in a quick search.

 

To be clear, apart from one Xeon I have, none of my Intel CPUs have enough L3 either. Oh, I have some Broadwells with L4 that work great too. I'm kinda hoping the core counts of Zen2 will enable a new level of performance that I can only dream of right now.

We don't have officially published numbers yet, as Rome hasn't been launched. The core arrangement is also still up in the air, though it's looking like the CCXs are gone. If true, there's a lot we don't know about the design and thus can't project out much about. (But it looks like 16mb per chiplet, so it should be 2mb per core.)

 

As for the I/O die, it'll have the memory controllers. If the information from the BIOS analysis is correct, each chiplet will have primary (or exclusive, not sure) access to the memory through an individual memory controller. Each chiplet with its own memory channel. But, that's bandwidth to the Memory. Interior bandwidth will be a lot higher.  Some of this is likely the response to the memory topology issues that could crop up with Epyc.

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53 minutes ago, Taf the Ghost said:

We don't have officially published numbers yet, as Rome hasn't been launched.

I wasn't sure how much info was out there, since it has been kinda announced, and there's been some leaks from the supercomputer crowd who are actually building with them.

Main system: i9-7980XE, Asus X299 TUF mark 2, Noctua D15, Corsair Vengeance Pro 3200 3x 16GB 2R, RTX 3070, NZXT E850, GameMax Abyss, Samsung 980 Pro 2TB, Acer Predator XB241YU 24" 1440p 144Hz G-Sync + HP LP2475w 24" 1200p 60Hz wide gamut
Gaming laptop: Lenovo Legion 5, 5800H, RTX 3070, Kingston DDR4 3200C22 2x16GB 2Rx8, Kingston Fury Renegade 1TB + Crucial P1 1TB SSD, 165 Hz IPS 1080p G-Sync Compatible

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3 hours ago, Stefan Payne said:

With AMD K8 the Memory Controller went into the CPU.
With Zen2 the Memory Controller was thrown out of the CPU.

Well, not precisely.  It's still on CPU, just not on the same die as the cores.  Technically speaking, the I/O die is still on the CPU.

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