Ryzen 3000 „Valhalla“

[CarlBar]

1 minute ago, hobobobo said:

AMD at the rome presentation said that numa is dead, that prolly why you have the impression.

 

Chiplets interconnect would probably be zen5, there was an insteresting point on anandtech(i think) about fragmenting i/o and memory controller between dies and having the current io die have just cash and logic to unify all dat i/o and memory. Considering my meager understanding of the hardware, im probably talking out of my ass, but seems interesting.

 

TR4 to have gpu die confirmed though

 

Ahhh thank you.

 

I  doubt it on putting IO on the chiplets. The entire point of going to a chiplet architecture is to get all the stuff that doesn't benefit from a smaller process node off said nod and leave it on an older higher yielding node whilst leaving the stuff that does benefit on the new node but spread amongst several smaller chips, (which improves yields).

[hobobobo]

1 minute ago, CarlBar said:

 

Ahhh thank you.

 

I  doubt it on putting IO on the chiplets. The entire point of going to a chiplet architecture is to get all the stuff that doesn't benefit from a smaller process node off said nod and leave it on an older higher yielding node whilst leaving the stuff that does benefit on the new node but spread amongst several smaller chips, (which improves yields).

Well, i understand that part, the idea of fragmenting mc and io comes mostly from 7nm maturing and costs of packaging vs costs of offloading io and mem to another die should more or less equal out. But then again, tsmc is on track to 5nm so it might be just futile musings.

[CarlBar]

3 minutes ago, hobobobo said:

Well, i understand that part, the idea of fragmenting mc and io comes mostly from 7nm maturing and costs of packaging vs costs of offloading io and mem to another die should more or less equal out. But then again, tsmc is on track to 5nm so it might be just futile musings.

 

Yeah the plan for AMD is to be on 5nm at Zen 4 if i recall the rome launch event slides correct. There's really no reason they'd ever be on a high yielding node long enough for that theroy to make sense unless they find themselves in the same kind of situation intel is in with 10nm ATM.

[hobobobo]

1 minute ago, VegetableStu said:

whoa, got a link? o_o

Nah, thats an empty statement, based on hopes, dreams and possible 3650x or whats the name of ryzen 3 with 20cu

[hobobobo]

1 minute ago, CarlBar said:

Yeah the plan for AMD is to be on 5nm at Zen 4 if i recall the rome launch event slides correct. There's really no reason they'd ever be on a high yielding node long enough for that theroy to make sense unless they find themselves in the same kind of situation intel is in with 10nm ATM.

In theory, they can split the chiplet stack even futher later, when they have some more cashflow, and use mature nodes for lowend/mobile/whatever. They already kinda split the stack with regular ryzens, g's and tr's. Perhaps, divergence of server and consumer hardware might force them into it, who knows.

[Taf the Ghost]

3 minutes ago, CarlBar said:

 

Yeah the plan for AMD is to be on 5nm at Zen 4 if i recall the rome launch event slides correct. There's really no reason they'd ever be on a high yielding node long enough for that theroy to make sense unless they find themselves in the same kind of situation intel is in with 10nm ATM.

5nm is an iteration of 7nm. So it's a shrink, but it's more like the 32/28nm days. Big changes are foundry 4nm. That's the next big jump and that should come with GAAfets.

[leadeater]

1 hour ago, CarlBar said:

 

Yeha but that relies on interconnects between ccx's, (or in the case chiplets), which we know rome doesn't have, (Ryzen/TR will apparently but i'd assume memory copies rome), so they can't be doing it that way because the only thing it can hop through is the IO die, it makes no sense to hop to the IO die to hop to another chiplet to hop back to the IO die to hop to the memory.

 

I also want to say i remember them saying NUMA is dead but i can't remember for 100% sure.

Actually the CCX's and memory controllers are independent on Zen/Zen+ and there is actually different kinds of InfinityFabric connection types being used, they all just use the same protocol that supports different transport layers.

 

Within a Zen/Zen+ die there are 2 CCXs which connect via IF through the L3 cache, this section is called the Scalable Data Fabric (SDF). The memory controller, I/O Hub and GMI controller connect to the SDF. All entities within a Zen/Zen+ die are independent and connect to the SDF, which is clock sync'd to the memory controller. Dies connect to each other through the GMI interconnects, also using IF protocol.

Spoiler

This means all cores in a die have equal access to both memory channels on the die, there is no bandwidth or latency penalty for any cores accessing any memory region. The inter core latency benchmarks that were done when Zen was launched is about latency between cores not memory. It's commonly misunderstood that the CCX's own or control a memory controller each which isn't the case. EPYC and Threaripper, or any Zen/Zen+ multi die design, rely on the GMI controllers and SDF not the CCX's. It's the best design possible without chiplet technology for a multi die CPU.

 

What's important for Zen2 and the I/O die is the actual internal layout and design. Is there a single very large SDF with 8 memory controllers connected to it as well as 8 GMI interfaces. Is that too big, with too many connection points making traces hard to layout, is there a downside to that. Or are there multiple modules (CCX like) in the I/O die that contain an SDF and some memory/GMI interfaces and then multiple of these are linked via the SDFs. The benefit there is you can scale that design for Ryzen, Threadripper and EPYC. You put in as many modules that are required for each platform, only need 2 channels for Ryzen? Then 1 module. Only need 4 or 6 for Threadripper, put in 2 or 3 modules. Need 8 channels for EPYC, put in 4 modules. Obvious downside is the internal SDF links.

 

I'm expecting the former I/O design not the latter but the latter is not without it's benefits, especially if the SDF connectivity is much faster and lower latency in Zen2.

 

Edit: Fixed image, source here FYI: https://en.wikichip.org/wiki/amd/microarchitectures/zen

[leadeater]

10 minutes ago, VegetableStu said:

Hopes shattered lol

[hobobobo]

2 hours ago, VegetableStu said:

Sowwy?

 

At least know this - a random stranger on the internet is sure that there is going to be an apu threadripper, probably 4/5th iteration, at the time they move to chiplet gpu on the enterprise level. Or perhaps right this generation if that ryzen 5 with 8c 20cu is real. Id actually happily bet heavily on the former and conservatively on the latter.

 

Another thing that makes me more or less sure - AMD saw the demand for Hades canyon and it was substentialy higher then for any previous nuc. All you need is a nano/pico-atx tr4 reference board design and oems and boardpartners will sweep the parts of the shelf

 

The dream would be 16c 20cu 8hi stack TR, which is more or less possible this gen, with imc rework though, but this would not happen

[Hellion]

On 3/20/2019 at 5:41 AM, Geography said:

It's been less than a year since the 2000 series...

 

Would you prefer they rush Ryzen 2 to market and have massive shortages like intel so that you can't buy a CPU at MSRP?