Ryzen 3000 „Valhalla“

[Stefan Payne]

6 minutes ago, Jito463 said:

Well, not precisely.  It's still on CPU, just not on the same die as the cores.  Technically speaking, the I/O die is still on the CPU.

Its on CPU Package, not monolithic. That's the point.

 

There was a similar thing in the Past...

 

Its called MMC-1:

https://en.wikipedia.org/wiki/MMC-1

And MMC-2:

http://www.cpu-world.com/CPUs/Pentium-II/Intel-Mobile Pentium II 266 MMC-1 - PMD26605002AB.html  or that:

http://www.cpu-world.com/CPUs/Pentium-II/Intel-Mobile Pentium II 400 MMC-2 - PMG40002001AA.html

 

 

MMC-1 is like this:

http://www.cpu-world.com/CPUs/Celeron/Intel-Mobile Celeron 400 MMC-1 - PMH40001001ES.html

 

Matisse is a so called "MCM"-> Multi Chip Module with a "Chipset" On Chip, not integg

[RejZoR]

For me it's all about the clocks. If they'll really be hitting 5GHz boost out of the box as rumors suggested, I'm probably buying one. A bit out of curiosity, a bit about future proofing and a bit because I really want AMD in my system again, it has been a very while since Athlon XP...

[MeatFeastMan]

You can tell it's getting very close to release now. There's a deal I just saw on scan (Don't remember seeing it before but if anyone has let me know) saying that if people buy ryzen 5 or ryzen 7 2000 series they get a free download of the division 2. They are trying to get rid of every last bit of stock, in preparation.

 

Now people have a dilemma. Division 2 paired with a ryzen 5 or 7 is very attractive if you like the game (It's had very good reception from what I've seen)

[leadeater]

6 hours ago, porina said:

Leadeater wont be the only one. For single chiplet CPUs that should make them more monolithic-like and help, but makes 2 chiplet sounds NUMA again... beyond that, I'm either misunderstanding the claims, or just need someone to draw a simple diagram of how stuff is connected. Logically I imagined an IO die going to ram and the rest, with up to two chiplets hanging off it. The concept of a chiplet having ram channels doesn't make sense to me in that context, unless the IO die is a glorified switch?

Point 6 doesn't make any sense to me, the I/O die has all the memory controllers and the chiplets link to the I/O die via IF links. At worst I can see it being like Intel Mesh where there is preferred memory channel paths to reduce latency but there is still direct access capability for other memory controllers. That's why Intel Mesh in instances is worse than Ring Bus and Dual Ring Bus but in others is better.

 

Going to need a lot of memory tests/benchmarks to understand what is actually going on.

[CarlBar]

6 hours ago, Taf the Ghost said:

We don't have officially published numbers yet, as Rome hasn't been launched. The core arrangement is also still up in the air, though it's looking like the CCXs are gone. If true, there's a lot we don't know about the design and thus can't project out much about. (But it looks like 16mb per chiplet, so it should be 2mb per core.)

 

As for the I/O die, it'll have the memory controllers. If the information from the BIOS analysis is correct, each chiplet will have primary (or exclusive, not sure) access to the memory through an individual memory controller. Each chiplet with its own memory channel. But, that's bandwidth to the Memory. Interior bandwidth will be a lot higher.  Some of this is likely the response to the memory topology issues that could crop up with Epyc.

 

2 hours ago, leadeater said:

Point 6 doesn't make any sense to me, the I/O die has all the memory controllers and the chiplets link to the I/O die via IF links. At worst I can see it being like Intel Mesh where there is preferred memory channel paths to reduce latency but there is still direct access capability for other memory controllers. That's why Intel Mesh in instances is worse than Ring Bus and Dual Ring Bus but in others is better.

 

Going to need a lot of memory tests/benchmarks to understand what is actually going on.

 

 

AMD explicitly said for rome at least that any single chiplet can if it absolutely needs to call on the full memory bandwidth of every memory channel on the IO die, (8 channels at 32000mhz or just over 200GB/s). I'd assume the same holds true of Ryzen so it probably is a preferred memory channel thing.

[CarlBar]

9 hours ago, Franck said:

Any word on if B450 will support these new SKU's ?

 

9 hours ago, RejZoR said:

Socket support yes, with so many cores it's more a matter of power delivery. I wouldn't go wild with the R7 3700X or R9 3800X or whatever they'll be called on B350 boards. But sticking a R5 3600X into B350 probably shouldn't be a big problem. We'll see when CPU's actually arrive tho...

 

No offence, (seriously), mr sheep but i think you left your brain in neutral. AMD demo'd an 8 core at CES, it only had the same TDP, (65w), as the existing Ryzen 5. So long as the B series motherboards can handle current R7's they probably can cope with the new R7'sn where going to get. though making any hard plans would be inadvisable.

 

Also super dumb question, got a tiachi ultimate MB, how do i check/do the bios update, (i haven't messed with a bios update since before UEFI was a thing)? Probably not going to be able to justify grabbing a 3000 series out the door but might as well make sure it's sorted next time i reboot.

[leadeater]

33 minutes ago, CarlBar said:

AMD explicitly said for rome at least that any single chiplet can if it absolutely needs to call on the full memory bandwidth of every memory channel on the IO die, (8 channels at 32000mhz or just over 200GB/s). I'd assume the same holds true of Ryzen so it probably is a preferred memory channel thing.

True but that doesn't mean access to all memory controllers is equal, as in latency wise. It really depends on how the IF links are attached to the memory controllers, we don't know the internal workings of the I/O die. Chiplet 1 could have 40ns to channel 1 but 60ns to channel 2 through 8.

 

I personally hope the IF's all attach in to a common memory controller logical layer and are single hop to all channels with closet path preference within that logic area, like Intel Mesh.

[Jito463]

6 hours ago, Stefan Payne said:

Its on CPU Package, not monolithic.

Yes, but that's not what you wrote.  I was simply responding to your post as written.

[CarlBar]

4 hours ago, leadeater said:

True but that doesn't mean access to all memory controllers is equal, as in latency wise. It really depends on how the IF links are attached to the memory controllers, we don't know the internal workings of the I/O die. Chiplet 1 could have 40ns to channel 1 but 60ns to channel 2 through 8.

 

I personally hope the IF's all attach in to a common memory controller logical layer and are single hop to all channels with closet path preference within that logic area, like Intel Mesh.

 

Oh sure, but i was addressing the questions about weather one chiplets might not be able to access a given memory channel at all. besides major screw ups aside the hugely increased frequancy of the IF links should shave a fair amount off the latency all by itself as it spends less time in hop that way.

[leadeater]

3 minutes ago, CarlBar said:

Oh sure, but i was addressing the questions about weather one chiplets might not be able to access a given memory channel at all. besides major screw ups aside the hugely increased frequancy of the IF links should shave a fair amount off the latency all by itself as it spends less time in hop that way.

Even in the Zen/Zen+ designs dies can access all memory channels, it's just that the path is multiple hops and bandwidth constrained a.k.a NUMA.

[Taf the Ghost]

3 minutes ago, leadeater said:

Even in the Zen/Zen+ designs dies can access all memory channels, it's just that the path is multiple hops and bandwidth constrained a.k.a NUMA.

It'll be interesting to see the improvements AMD brought forward with regards to memory. The chiplet penalty should be extremely small just due to physical distance being almost no different.

 

Which reminds me, @porina , there should be 32mb of L3 Cache per chiplet. How things are aligned is still up in the air. AMD has done something with the CCX approach, but precisely "What" is still unknown. Could be as simple as a pair of CCX with a direct crossbar between their L3 Caches. Or some center-line "ring" connecting the two CCX together.

[leadeater]

12 minutes ago, Taf the Ghost said:

Or some center-line "ring" connecting the two CCX together.

lol CCX Ring Bus 

 

[Taf the Ghost]

1 minute ago, leadeater said:

lol CCX Ring Bus 

8 core chiplet with a Ring would make a lot of sense. That's not a joke, haha.

[leadeater]

2 minutes ago, Taf the Ghost said:

That's not a joke, haha.

Well you know me by now, every chance to make a terrible joke or pun 

[Taf the Ghost]

11 minutes ago, leadeater said:

Well you know me by now, every chance to make a terrible joke or pun 

I still think it's probably a 2 CCX per die alignment, but they've probably improved the interaction between them. We'll find out, as 8 cores in one core complex would favor a Ring Bus. Which probably means I need to check the technical name for that type of bus that AMD will call it, rather than Ring Bus.

[leadeater]

38 minutes ago, Taf the Ghost said:

Which probably means I need to check the technical name for that type of bus that AMD will call it, rather than Ring Bus.

Round Bus

Circular Bus

.

.

.

.

Bus Ring

Spoiler

 

[williamcll]

What motherboards will support the new chips?

[porina]

3 hours ago, Taf the Ghost said:

Which reminds me, @porina , there should be 32mb of L3 Cache per chiplet.

 

15 hours ago, Taf the Ghost said:

(But it looks like 16mb per chiplet, so it should be 2mb per core.)

Which is it?  32MB per socket perhaps? That's kinda my hope even for a 12 core version, but bandwidth between chiplets is the concern. If 32MB per chiplet after all, that would just crush my workloads.

[Taf the Ghost]

2 minutes ago, porina said:

 

Which is it?  32MB per socket perhaps? That's kinda my hope even for a 12 core version, but bandwidth between chiplets is the concern. If 32MB per chiplet after all, that would just crush my workloads.

16mb per CCX; 32mb per chiplet. I was confusing myself a bit. At least if the fairly consistent rumor of double the L3 is true.

[Quadriplegic]

13 hours ago, MeatFeastMan said:

You can tell it's getting very close to release now. There's a deal I just saw on scan (Don't remember seeing it before but if anyone has let me know) saying that if people buy ryzen 5 or ryzen 7 2000 series they get a free download of the division 2. They are trying to get rid of every last bit of stock, in preparation.

 

Now people have a dilemma. Division 2 paired with a ryzen 5 or 7 is very attractive if you like the game (It's had very good reception from what I've seen)

That deal has been around for basically couple of months by now.

[LukeSavenije]

i only have one feeling about this

[Bearded_Ed]

2 hours ago, williamcll said:

What motherboards will support the new chips?

In theory... all existing boards should.... Whether they will or not is the question.  As someone with an Asus TUF B350M.  I am very much hoping that we will get support.

 

[RejZoR]

13 hours ago, CarlBar said:

 

 

No offence, (seriously), mr sheep but i think you left your brain in neutral. AMD demo'd an 8 core at CES, it only had the same TDP, (65w), as the existing Ryzen 5. So long as the B series motherboards can handle current R7's they probably can cope with the new R7'sn where going to get. though making any hard plans would be inadvisable.

 

Also super dumb question, got a tiachi ultimate MB, how do i check/do the bios update, (i haven't messed with a bios update since before UEFI was a thing)? Probably not going to be able to justify grabbing a 3000 series out the door but might as well make sure it's sorted next time i reboot.

Nah, my brain is fine. Basically, the easiest way is to check what was the most powerful CPU you could stick in it on release day. If it was Ryzen 1800X, then any CPU with same power design would work fine in it assuming it doesn't have other compatibility issues with the board.

 

I mean, few years back we didn't have such huge jumps between series in terms of core count. But socket is remaining the same, with AMD at least. It's smart to check compatibility first. CPU does fit, but if it works well is another thing. I mean, higher end X series boards are known to have cheapo VRM's, B series are probably cheapened even further...

[CarlBar]

8 hours ago, leadeater said:

Even in the Zen/Zen+ designs dies can access all memory channels, it's just that the path is multiple hops and bandwidth constrained a.k.a NUMA.

 

Yeha but that relies on interconnects between ccx's, (or in the case chiplets), which we know rome doesn't have, (Ryzen/TR will apparently but i'd assume memory copies rome), so they can't be doing it that way because the only thing it can hop through is the IO die, it makes no sense to hop to the IO die to hop to another chiplet to hop back to the IO die to hop to the memory.

 

I also want to say i remember them saying NUMA is dead but i can't remember for 100% sure.

[hobobobo]

6 minutes ago, CarlBar said:

 

Yeha but that relies on interconnects between ccx's, (or in the case chiplets), which we know rome doesn't have, (Ryzen/TR will apparently but i'd assume memory copies rome), so they can't be doing it that way because the only thing it can hop through is the IO die, it makes no sense to hop to the IO die to hop to another chiplet to hop back to the IO die to hop to the memory.

 

I also want to say i remember them saying NUMA is dead but i can't remember for 100% sure.

AMD at the rome presentation said that numa is dead, that prolly why you have the impression.

 

Chiplets interconnect would probably be zen5, there was an insteresting point on anandtech(i think) about fragmenting i/o and memory controller between dies and having the current io die have just cash and logic to unify all dat i/o and memory. Considering my meager understanding of the hardware, im probably talking out of my ass, but seems interesting.

 

TR4 to have gpu die confirmed though