CXL 1.0 Specification released

[CarlBar]

6 hours ago, LukeSavenije said:

according to anandtech writer Ian Cutress it's 5.0 both in the whole article and the attached pictures... so I'm not sure if it's a typo

 

The point is unless there's been some sudden movement since i last looked it can't be PCI-E 5.0 because PCI-E 5.0 does not exist. There's nothing to base it off or make it compatible with.It would be like someone claiming in 1975 that they had a x86 compatible processor. The famous 8086 was undoubtedly in development at the time, (from what i can tell), and someone using the older 8 bit processor it was an expansion of might be able to come up with somthing close. But since design work on the 8086 was still ongoing it was practically speaking impossible to make somthing x86 compatible in 1975 because x86 hadn't been defined as a standard at the time.

[porina]

19 minutes ago, CarlBar said:

The point is unless there's been some sudden movement since i last looked it can't be PCI-E 5.0 because PCI-E 5.0 does not exist.

PCIe 5.0 has existed as a published draft to PCI-SIG members since 2017 so it isn't unknown, just not finalised yet. 

 

Before writing off any of these interconnects, I think we need to understand the real difference between them, beyond the names. They may be optimised differently for different scenarios and there may not be one single "best" one.

[Thaldor]

Am I the only one who let's air out heavily because one more connector to PC that leaks your data out like Facebook? It's not even month since it was found that the Thunderbolt has the same exact problem as the Firewire has had for all these years and in both cases the culprit is that they are PCIe based and so have direct lane to RAM. And now everyone is thinking it will be a great idea to have couple more connectors which are all PCIe based and "only for additional hardware"  * .

 

* "This port may also allow devices to directly change and copy things out of your RAM, if you care for your privacy and don't need this one, please add generous amount of superglue to patch this flaming hole in your cyber security"

[Stefan Payne]

Here some Articles that leads one to believe that Rome could come with CCIX:

 

https://www.servethehome.com/xilinx-alveo-u280-launched-possibly-with-amd-epyc-ccix-support/

https://www.anandtech.com/show/13578/naples-rome-milan-zen-4-an-interview-with-amd-cto-mark-papermaster

 

One potentially spoilered by Xilinx (those are the ones I meant), one by Papermaster

 

[leadeater]

1 hour ago, porina said:

PCIe 5.0 has existed as a published draft to PCI-SIG members since 2017 so it isn't unknown, just not finalised yet. 

 

Before writing off any of these interconnects, I think we need to understand the real difference between them, beyond the names. They may be optimised differently for different scenarios and there may not be one single "best" one.

And it's not unlikely that some of them will merge one day.

[Mira Yurizaki]

2 hours ago, Thaldor said:

Am I the only one who let's air out heavily because one more connector to PC that leaks your data out like Facebook? It's not even month since it was found that the Thunderbolt has the same exact problem as the Firewire has had for all these years and in both cases the culprit is that they are PCIe based and so have direct lane to RAM. And now everyone is thinking it will be a great idea to have couple more connectors which are all PCIe based and "only for additional hardware" 

This is a problem with the DMA system in general.  Except what are you going to do? DMA is one of the more fundamental performance enhancements for computer systems.

 

Besides that, DMA attacks require physical access to hardware. If an attacker has physical access, you can pretty much assume the game is over.

[Thaldor]

14 minutes ago, Mira Yurizaki said:

This is a problem with the DMA system in general.  Except what are you going to do? DMA is one of the more fundamental performance enhancements for computer systems.

 

Besides that, DMA attacks require physical access to hardware. If an attacker has physical access, you can pretty much assume the game is over.

Considering there doesn't seem to be critical need for faster port since thunderbolt already is good enough, there could be good calm to develope a better solution and while on it fix couple earlier mistakes. How that is done, I don't have a glue, goes so far off from my knowledge.

 

Attack side there's physical access and there's physical access. It's quite a lot different case if you have a port that allows RAM dump directly than not having one and needing to open the machine. Things are a lot easier if you can get RAM dump with encryption keys, that's why still some people get Epoxy ready if they notice Firewire ports and now thunderbolt ports too, of course there's other ways to get those and fancy pansy things to try, but they ain't as easy as sticking a device in and "vóla, doesn't matter wether or not your disks were encrypted". And yes, cold-booting is another way, but that goes to the class of "fancy pansy" things to try.

 

Not really something that the general population should care, but if this is the way things are going to go we will soon have so less security that it really doesn't matter do you have a password or not.

[CarlBar]

3 hours ago, porina said:

PCIe 5.0 has existed as a published draft to PCI-SIG members since 2017 so it isn't unknown, just not finalised yet. 

 

 

Not finalised is effectively the same as non-existent though. Until it's finalised things can and will change. There is no "current" PCI-E 5.0 standard until it's finalized and the final specification is published. All your really saying is what i allready said with the x86 example, it's been worked on and a WIP version exists but the standard itself doesn't yet.

[williamcll]

As long as there are adaptors for PCI-E to CXL I'm completely fine with changing. 

[S w a t s o n]

1 hour ago, CarlBar said:

 

Not finalised is effectively the same as non-existent though. Until it's finalised things can and will change. There is no "current" PCI-E 5.0 standard until it's finalized and the final specification is published. All your really saying is what i allready said with the x86 example, it's been worked on and a WIP version exists but the standard itself doesn't yet.

U wot? No it's definitely not, PCIe 5.0 spec is in development alongside this spec but it's not the same as non-existent, things can be developed in tandem and PCIe 5 is already nearing finalization

[S w a t s o n]

47 minutes ago, williamcll said:

As long as there are adaptors for PCI-E to CXL I'm completely fine with changing. 

No adapters needed that's sort of the point (sort of)

[leadeater]

1 hour ago, Thaldor said:

Considering there doesn't seem to be critical need for faster port since thunderbolt already is good enough, there could be good calm to develope a better solution and while on it fix couple earlier mistakes. How that is done, I don't have a glue, goes so far off from my knowledge.

 

Attack side there's physical access and there's physical access. It's quite a lot different case if you have a port that allows RAM dump directly than not having one and needing to open the machine. Things are a lot easier if you can get RAM dump with encryption keys, that's why still some people get Epoxy ready if they notice Firewire ports and now thunderbolt ports too, of course there's other ways to get those and fancy pansy things to try, but they ain't as easy as sticking a device in and "vóla, doesn't matter wether or not your disks were encrypted". And yes, cold-booting is another way, but that goes to the class of "fancy pansy" things to try.

 

Not really something that the general population should care, but if this is the way things are going to go we will soon have so less security that it really doesn't matter do you have a password or not.

None of these interconnects CXL, CCIX, Gen-Z etc actually apply to any desktop computers though. You will never see it come across the server divide.

 

As for the need for DMA, yes this is critical even for desktops. You simply will not get high speed anything without DMA, and you can secure DMA anyway. It's not a critical unsolvable flaw and even removing it does not mean there isn't another way to exploit the system through that port or protocol and if you develop something else, new, how do you know that doesn't have security flaws in it either?

 

Things like the PCIe spec require DMA to be present because some devices and use cases need it, you don't however have to implement it on your device. CXL, CCIX and Gen-Z don't exist without direct memory access, 100Gb/400Gb Ethernet isn't possible without DMA.

 

If we get rid of all DMA then at least there would be a point to 18 core massive clock CPUs, you'd need it just to transfer files from an SSD to an external USB3.1/Thunderbolt drive or use an external GPU, have decent wireless performance although with massive latency.

[Taf the Ghost]

11 hours ago, Mira Yurizaki said:

To add it's not like AMD can leverage other fabs outside of TSMC, since GF stopped their 7nm development and Samsung is the only other company that can do it (as far as I know), and they've got other things to worry about.

 

So either AMD has to release Rome at a larger fab processor is just deal with low supply.

It wouldn't be "low" supply, but it would take a decade for AMD to hit 50% of x86 market share. And they'd end up buying half of TSMC to do it in the process. There's a reason Intel went about murdering AMD out of so many markets in the 2000s.

[porina]

8 hours ago, CarlBar said:

Not finalised is effectively the same as non-existent though. Until it's finalised things can and will change. There is no "current" PCI-E 5.0 standard until it's finalized and the final specification is published. All your really saying is what i allready said with the x86 example, it's been worked on and a WIP version exists but the standard itself doesn't yet.

You can't go from nothing to released spec. Organisations involved with the development of the spec have to have something to work on, which is the draft. According to what public info I can find, the release of 5.0 spec is due any time now. Parties actively involved with its development have a good idea what it will be.

[cj09beira]

13 hours ago, Mira Yurizaki said:

To add it's not like AMD can leverage other fabs outside of TSMC, since GF stopped their 7nm development and Samsung is the only other company that can do it (as far as I know), and they've got other things to worry about.

 

So either AMD has to release Rome at a larger fab processor is just deal with low supply.

if they want too amd can certainly use samsung, and they probably will with zen 3

[cj09beira]

7 hours ago, leadeater said:

None of these interconnects CXL, CCIX, Gen-Z etc actually apply to any desktop computers though. You will never see it come across the server divide.

 

As for the need for DMA, yes this is critical even for desktops. You simply will not get high speed anything without DMA, and you can secure DMA anyway. It's not a critical unsolvable flaw and even removing it does not mean there isn't another way to exploit the system through that port or protocol and if you develop something else, new, how do you know that doesn't have security flaws in it either?

 

Things like the PCIe spec require DMA to be present because some devices and use cases need it, you don't however have to implement it on your device. CXL, CCIX and Gen-Z don't exist without direct memory access, 100Gb/400Gb Ethernet isn't possible without DMA.

 

If we get rid of all DMA then at least there would be a point to 18 core massive clock CPUs, you'd need it just to transfer files from an SSD to an external USB3.1/Thunderbolt drive or use an external GPU, have decent wireless performance although with massive latency.

well i would love me some gen-z on my desktop 

[Techsharky360]

Some folks at work found this.  Not to sow the seeds of competition or anything.  Just a different slant on the idea.

 

https://www.techquila.co.in/intel-cxl-xe-graphics-cards/

 

[pas008]

On 3/12/2019 at 4:58 AM, porina said:

You can't go from nothing to released spec. Organisations involved with the development of the spec have to have something to work on, which is the draft. According to what public info I can find, the release of 5.0 spec is due any time now. Parties actively involved with its development have a good idea what it will be.

this could be like displayport 1.5 or whatever

hdmi 2.1 spec released and we havent seen new dp version for yrs

could be they need to rework it or some other standard will take over

[Results45]

On 3/12/2019 at 3:23 AM, cj09beira said:

well i would love me some gen-z on my desktop 

On 4/9/2019 at 5:52 PM, Techsharky360 said:

Some folks at work found this.  Not to sow the seeds of competition or anything.  Just a different slant on the idea.

 

https://www.techquila.co.in/intel-cxl-xe-graphics-cards/

 

Good find! 

 

Well here's Linus gaming on a system with PCIe 4.0:

 

According to TechSpot, PCIe 4.0 with data transfer rates up to 31.5 GB/s will be arriving in motherboards this year while PCIe 5.0 at 63 GB/s is being integrated into the server/supercomputing ecosystem first then consumer products a year or two later.

 

Regarding the TechQuila article I think it's valid to assume that Intel is developing a CXL-integrated of NV-Link to allow people sync 2 or more "Xe" cards together.

 

On 3/11/2019 at 7:43 PM, leadeater said:

None of these interconnects CXL, CCIX, Gen-Z etc actually apply to any desktop computers though. You will never see it come across the server divide.

Spoiler

 

As for the need for DMA, yes this is critical even for desktops. You simply will not get high speed anything without DMA, and you can secure DMA anyway. It's not a critical unsolvable flaw and even removing it does not mean there isn't another way to exploit the system through that port or protocol and if you develop something else, new, how do you know that doesn't have security flaws in it either?

 

Things like the PCIe spec require DMA to be present because some devices and use cases need it, you don't however have to implement it on your device. CXL, CCIX and Gen-Z don't exist without direct memory access, 100Gb/400Gb Ethernet isn't possible without DMA.

 

If we get rid of all DMA then at least there would be a point to 18 core massive clock CPUs, you'd need it just to transfer files from an SSD to an external USB3.1/Thunderbolt drive or use an external GPU, have decent wireless performance although with massive latency.

 

.

 

I think some form of enterprise CXL technology will make it into Intel consumer GPUs ~ just like how Nvidia combines multiple NV-Link connections for 300 GB/s interconnections in it's DGX machines. As for the others I'm not so sure unless other hardware R&D/manufacturers decide to build consumer products rivaling NV-Link and Xe+CXL.

 

Also here's a neat comparison of bi-directional data transfer rates between different interconnect technologies:

• NV-Link: 300 GB/s
• CXL: ???
• Gen-Z: 64 GB/s to 800 GB/s
• CCIX: 64 GB/s to 100 GB/s
• OpenCAPI 3.0: 50GB

[FPSwithaWacomTablet]

Soo... Another bus arbiter for PCI Express? Or are we talking more like a PCI Express network where each device is attached to a networked CXL node?