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Ryzen 3000 Leaks

Deus Voltage
1 minute ago, Mihle said:

I bet they have chiplets and IO die as Epyc Rome does. One 14nm IO die with 2 7nm chiplets, 8 core max each. It would make the leak make much more sense. IO is less bonuses scaling down and its harder to scale them down.

Not saying the leak is true, just saying it isnt necessary false. (I personally bet core count is correct but clock speed isnt)
We just have to wait and see,

If they were going to be glueing chips together essentially then they would more than likely need a different socket.

 

They are able to jam more cores on the chips now due to process shrink to 7nm.

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5 minutes ago, AngryBeaver said:

If they were going to be glueing chips together essentially then they would more than likely need a different socket.

 

They are able to jam more cores on the chips now due to process shrink to 7nm.

Why do you think they need a different socket?

 

The I/O chip should be able to be layout to electrically fit into at AM4 socket, and due to the core chips being 7nm I can see it physically fitting on the package with 2 7nm + 1 14nm dies

 

Spoiler

1800x delid, their is extra width that can be used.

bcfa43d95802.jpg

 

if you want to annoy me, then join my teamspeak server ts.benja.cc

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I have not read the entire thread, so please forgive me if this has already been asked. Do we have an idea when these new CPUs will be available to purchase?

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I would be very interested in yield data. Like how much Threadripper do they get on a single wafer (I'd guess 1-2) and how many Ryzen and Athlons (if they will ever be made at 7nm).

Folding stats

Vigilo Confido

 

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1 minute ago, The Benjamins said:

Why do you think they need a different socket?

 

The I/O chip should be able to be layout to electrically fit into at AM4 socket, and due to the core chips being 7nm I can see it physically fitting on the package with 2 7nm + 1 14nm dies

Because all of those pins are mapped to a function.. while it might be theoretically possible it would not be efficient and it wouldn't make much sense. They would be better off going with a new socket in that situation. So those pins instead of directly mapping to 1 die would need to map to 2 or even 3 in your example. That means you are going to need to make some sacrifices in how quickly signals can move from pin to the corresponding process. You would have a scenario similar to the high end threadripper except it would be for everything and not just PCI-E lanes. So this would mean that all information would go to Die 1 and then Die 1 would send it to Die2, which would then need to go back to DIE 1 and exit to the motherboard. That causes delays even if just in nanoseconds.

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51 minutes ago, TigerHawk said:

Same. I feel like some of the information may be accurate but on the wrong SKU.

 

Take the 3600X for example

 

Ryzen 5 3600X: 8C/16T //  Base: 4.0 GHz //  Boost: 4.8 GHz // 95 W TDP // Price: 229$

 

now change it into this

 

Ryzen 7 3700X: 8C/16T //  Base: 4.0 GHz //  Boost: 4.8 GHz // 95 W TDP // Price: 329$

 

Suddenly its a lot more believable as a SKU. It is a reasonable upgrade over the previous gen and I'd say still a good buy for people looking to upgrade.

 

With this lineup, there are none that don't have SMT enabled. There is no way they would just trash all the CPUs with the SMT module that didn't form correctly. That is the entire reason you get CPUs like Ryzen 3 1200s with 4 cores 4 threads and such. It's a way to still make money off of dies that had about 60-70% of it malformed in the manufacturing process.

actually there is no such thing as a smt module, smt uses the same core, skus with smt disabled do it exclusively to segment the products better nothing else.

44 minutes ago, AngryBeaver said:

This is from another thread on this topic, but I think it is relevant here. My apologies Turtle for cross quoting.

 

See the items I highlighted in red. Look at the base clocks. I can understand them wanting to raise the boost clocks on higher end models, but the base clock doesn't make sense.

 

As core count increases normally you see a lower base clock, because of the amount of heat and power generated on these chips when all cores are running full out. The base clock is the lowest clocks would drop in that scenario. Lets compare it to their threadripper line which would be the best comparison to this.

 

image.png.fa9eb10b6e4002300f17788ba1b34d27.png

 

As core count is reduced we see the base block come up as well as the boost clock... the only exception is the 2920x and I think this was more of a pricing move to push people to the 2950x. I marked out the older threadrippers. But if you look you will see the base clock works the same way there.

 

This is why I believe all of this "Leaked" information is all make up crap. There might be a slight grain of truth somewhere, but it isn't on actual cpu specs.

the thing here is that with chiplets amd can bin the dies much more, thus they can get better performance by using the best silicon possible, this will also mean that max oc will be even more tied to what sku you buy 

2 minutes ago, Crosseyed Sniper said:

I have not read the entire thread, so please forgive me if this has already been asked. Do we have an idea when these new CPUs will be available to purchase?

announcement on CES 2019, release we don't really know, it might be late Q1 early Q2

 

3 minutes ago, AngryBeaver said:

Because all of those pins are mapped to a function.. while it might be theoretically possible it would not be efficient and it wouldn't make much sense. They would be better off going with a new socket in that situation. So those pins instead of directly mapping to 1 die would need to map to 2 or even 3 in your example. That means you are going to need to make some sacrifices in how quickly signals can move from pin to the corresponding process. You would have a scenario similar to the high end threadripper except it would be for everything and not just PCI-E lanes. So this would mean that all information would go to Die 1 and then Die 1 would send it to Die2, which would then need to go back to DIE 1 and exit to the motherboard. That causes delays even if just in nanoseconds.

the whole point of the IO die is to tie everything together, from the socket to the compute dies will only go vcore vsoc and ground connections, all data lines from the socket will pass directly to the IO die, that then will talk to the compute dies, thus there is no problem in making it work on am4

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1 minute ago, AngryBeaver said:

Because all of those pins are mapped to a function.. while it might be theoretically possible it would not be efficient and it wouldn't make much sense. They would be better off going with a new socket in that situation. So those pins instead of directly mapping to 1 die would need to map to 2 or even 3 in your example. That means you are going to need to make some sacrifices in how quickly signals can move from pin to the corresponding process. You would have a scenario similar to the high end threadripper except it would be for everything and not just PCI-E lanes. So this would mean that all information would go to Die 1 and then Die 1 would send it to Die2, which would then need to go back to DIE 1 and exit to the motherboard. That causes delays even if just in nanoseconds.

AFAIK they way Epyc 2 is laid out, which I would expect Ryzen 3000 to be the same, is that all socket pins go to the 14nm I/O die, then it "manages" traffic to the 7nm core dies, making it where 1 die is only connected to the motherboard, unlike Epyc 1. which again would make designing a new socket not needed.

 

I can see a new shipset for power on the rumored 3800x/3850x, but the socket would be the same. (unless they want to make it impossible to put a high TDP part in a under powered board, but that is more keying then full redesign)

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I am soo stoked to build with that Ryzen 9! I don't know how they will preform but I hope it is amazing like the other CPUs they have there.

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8 minutes ago, cj09beira said:

actually there is no such thing as a smt module, smt uses the same core, skus with smt disabled do it exclusively to segment the products better nothing else.

the thing here is that with chiplets amd can bin the dies much more, thus they can get better performance by using the best silicon possible, this will also mean that max oc will be even more tied to what sku you buy 

announcement on CES 2019, release we don't really know, it might be late Q1 early Q2

 

the whole point of the IO die is to tie everything together, from the socket to the compute dies will only go vcore vsoc and ground connections, all data lines from the socket will pass directly to the IO die, that then will talk to the compute dies, thus there is no problem in making it work on am4

Binning them is fine, but that would apply more to boost clocks. So for example we are talking about say the R9 with a TDP of 135W... there is no way it is going to be anywhere near spec at those base clocks. They do have to stay close to those specs for normal operations. Which is why that base clock doesn't make sense. Now if someone wants to turn on enhancements on the motherboard to let it always maintain boost clocks on all cores that is fine.

 

As to the chiplets and the multi die idea... has there been anything to suggest they are moving to this on the consumer platform. It makes sense on the servers and enthusiast platforms, but I don't feel it is warranted on anything consumer side. It will add latency even if small.

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20 minutes ago, AngryBeaver said:

Binning them is fine, but that would apply more to boost clocks. So for example we are talking about say the R9 with a TDP of 135W... there is no way it is going to be anywhere near spec at those base clocks. They do have to stay close to those specs for normal operations. Which is why that base clock doesn't make sense. Now if someone wants to turn on enhancements on the motherboard to let it always maintain boost clocks on all cores that is fine.

 

As to the chiplets and the multi die idea... has there been anything to suggest they are moving to this on the consumer platform. It makes sense on the servers and enthusiast platforms, but I don't feel it is warranted on anything consumer side. It will add latency even if small.

The cost to design 2 different CPU dies + 1 I/O die vs 1 CPU die + 2 I/O dies.

 

I would expect a 2 I/O dies of a proven process to be a lot simpler and cheaper then another CPU die with I/O on die. Also the chiplet design would allow for more options for APUs with out making to many dies. they can cover a wider product stack with interchangeable I/O dies.

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12 minutes ago, AngryBeaver said:

Binning them is fine, but that would apply more to boost clocks. So for example we are talking about say the R9 with a TDP of 135W... there is no way it is going to be anywhere near spec at those base clocks. They do have to stay close to those specs for normal operations. Which is why that base clock doesn't make sense. Now if someone wants to turn on enhancements on the motherboard to let it always maintain boost clocks on all cores that is fine.

 

As to the chiplets and the multi die idea... has there been anything to suggest they are moving to this on the consumer platform. It makes sense on the servers and enthusiast platforms, but I don't feel it is warranted on anything consumer side. It will add latency even if small.

its not only boost clocks, its the same thing as a good or bad vega gpu, if you get a good one you might be able to set something like a -100mv (even more) offset and save quite a bit of power at the same performance. now chiplets allow amd to more easily bin the chips so that they save the best for those higher core count products, thus allowing for higher clocks and also help keep tdp lower than if they made the cpu monolithic (at still 16cores, even at 8 this is better). adore went over this.

 

say amd made 10M dies of each cpu die they make, the apu die zepplin, and the top 5% can do 4.3Ghz at tdp, thats 0.5M dies, but say the top 2% can do 4.45ghz at tdp, but thats only 0.2M dies which lets say its enough for such a sku to make sense, but what if amd used the same die for all of the skus, then the top 2% would get 0.4M and that might be enough dies for a new sku, 

 

yes it will add latency but saves amd millions of dollars in design costs, which they really need to save, allows them to clock the chips higher, increases yields, etc

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12 hours ago, Crunchy Dragon said:

6c/12t on Ryzen 3 seems a little far fetched, personally.

Seeing as they are already selling the 2600 for 160 it's not that big of a jump to sell a 6c/12t for r3 prices. 

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interesting, it's not wccf sourced stuff, so it's believable lol

Details separate people.

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10 hours ago, GoldenLag said:

another interesting thing is that AMD should have a 5% IPC advantage if the IPC gains are remotely true.

 

im still a bit skeptical about the clockspeed of these chips, among other things, though it seems to check out

I think it might be like what we have currently with the 2700x. It says it's boost clock is 4.3 ghz but realistically you can expect 4.2 to 4.1 as an all core overclock. That would put these at the 4.9 to 4.8 ghz overclock range which isn't too far fetched. 

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This is looking way to good! I'd definitely hope to see it become reality, but we'll have to be patient, wait and see retail chips tested. 

Architectural improvement, along node improvements, together sure brings a great improvement. We expected higher IPC increase and definitely clocks for this series, but this jump, along core count increase is just looking way too appealing. If it all ends up like so of course and the price too!

What I knew they'd do is doubling the core count per CCX specially makes sense, latency wise and how more things are multi-threaded too so it matters and it's a single die too.

 

We've seen 7nm Epyc dies shot and the 7nm chiplet design along with 14nm I/O is pretty awesome. Cost wise it's good, better yields and doubling the core count on AM4 package is looking possible no doubt. Just that makes you think how much of a jump they did over generations on new platforms.

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2 hours ago, AngryBeaver said:

This looks like something you would find on WccfTech. The clock speeds alone make me pretty sure this is fake. They aren't going to move from 2 generations of pretty hard caps to a 3rd gen where that magically disappears. You also aren't going to see boost speeds keep increasing as the core count goes up. If those boost are valid on the 16c then they would have no reason to not use them on a 8 core. They are trying to pull ahead of intel across the board, so that doesn't make sense.

 

I am willing to put money on the fact this is completely fake.

 

Unfortunately reddit has shown similar leaks and Adored.tv has a good track record. it;s also a flat given that where going to see some core count jump. Thats just how AMD has gone the last few gens.

 

2 hours ago, AngryBeaver said:

This is from another thread on this topic, but I think it is relevant here. My apologies Turtle for cross quoting.

 

See the items I highlighted in red. Look at the base clocks. I can understand them wanting to raise the boost clocks on higher end models, but the base clock doesn't make sense.

 

As core count increases normally you see a lower base clock, because of the amount of heat and power generated on these chips when all cores are running full out. The base clock is the lowest clocks would drop in that scenario. Lets compare it to their threadripper line which would be the best comparison to this.

 

image.png.fa9eb10b6e4002300f17788ba1b34d27.png

 

As core count is reduced we see the base block come up as well as the boost clock... the only exception is the 2920x and I think this was more of a pricing move to push people to the 2950x. I marked out the older threadrippers. But if you look you will see the base clock works the same way there.

 

This is why I believe all of this "Leaked" information is all make up crap. There might be a slight grain of truth somewhere, but it isn't on actual cpu specs.

 

Whilst i've allready expressed my doubts about some of the TDP's the new node halves thermals at the same core count and frequencies and we know simple architecture improvments will produce at least a 3-4% boost clock gain on top of any node based frequency uplift because thats what zen+ managed.

 

1 hour ago, TigerHawk said:

I don't think so. I think they would just not want to cannibalize the threadripper platform by putting too many cores on regular desktop.

 

Unless, that is, they are planning to do away with HEDT altogether and kill threadripper off. Just go Ryzen and EPYC. Maybe reuse the threadripper name for R9s or something.

 

And why is treading on threadripper 2 an issue? First release is supposed to be computex, over 6 months from now. Second new threadripper 3's will be coming. Again i don't see an issue here.

 

1 hour ago, AngryBeaver said:

Also looking at the 16core R9 3850x vs the 2950x Threadripper. Look at the TDP requirements. I know the smaller process will reduce the power requirements, but they are also increasing the clocks which will counter-act that.. so we have the R9 using only 135w TDP vs the 180 of the 2950x?  That also doesn't seem realistic.

 

The R7 and R9 numbers are definitely dodgy, but so is the 9900K's 95w TDP so there's nothing really earth shattering about the idea. 135w for the R7's and 180ish for the R9's sounds more reasonable for me, but neither is unmanageable and they fit with the rumours you'll need an x570 for the R9's.

 

1 hour ago, AngryBeaver said:

If they were going to be glueing chips together essentially then they would more than likely need a different socket.

 

They are able to jam more cores on the chips now due to process shrink to 7nm.

 

It's Zen2 architecture. it will be a chiplet design because thats what the zen 2 architecture is, chiplets.

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more I think about this

more I can see this completely being true

 

eypc to ryzen 1/4 the cores

frequency from node improvement all around 7mm and not lp

ipc rumors of 29% being shot down from amd saying only to say in certain areas makes me think they could have increased only some or included avx 512 and an offset

 

pricing i'm very unsure of

I dont think they will give these away

lisa said before she wants higher priced products

so I think those are lowballs

 

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I feel the clock speed numbers are a bit inflated, if it can hit these numbers that would be amazing.

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8 minutes ago, ThePD said:

I feel the clock speed numbers are a bit inflated, if it can hit these numbers that would be amazing.

sandy bridge was 32nm and many peeps was able to hit 5ghz

refined node should give more frequency by far

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1 minute ago, pas008 said:

sandy bridge was 32nm and many peeps was able to hit 5ghz

I want to believe the hype but I try not to get too carried away.. If the leak is accurate, I will be upgrading from a i7-5820k

 

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It's looking promising, well priced too, if the leaks are true. I'll wait and see...

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8 minutes ago, ThePD said:

I want to believe the hype but I try not to get too carried away.. If the leak is accurate, I will be upgrading from a i7-5820k

 

I will upgrade if my work and fun performance increases

so single core needs to be increased pretty much and thats stock vs stock with oc vs oc variables with my 8700k

havent really had amd rig since 955be

almost went 2700x but many things I do wouldnt have been upgrade from 4770k single core wise

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37 minutes ago, ThePD said:

I feel the clock speed numbers are a bit inflated, if it can hit these numbers that would be amazing.

 

There's absolutely no reason they shouldn't be able to hit these numbers. For some reason i forgot the R7 1800x was a thing earlier. A 3.6Ghz base clock upped 20% is 4.32Ghz without any binning edge. The 4Ghz boost clock only works out 4.8 Ghz boost. BUT, Zen+ saw the Boost clock rise by an additional 4% or so over the expected increase based on base clock change, add that in and you land right on 5Ghz. Throw in binning advantages and 5.1Ghz is doable. Nothing stated here is implausible (other than R7/R9 TDP's), given everything we know about the new node capabilities. It's just eyebrow raising to see them pushing both frequency and core count, but there's little reason they couldn't do it from a technical PoV.

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I think I might be going Ryzen. These specs are impressive! 

I like zip-tying Intel stock coolers on graphics cards.

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10 hours ago, cj09beira said:

thing is we do have numbers on how it should perform from epyc testing on 4 channel, and its not that bad.

btw did you notice that the difference between navi 12 and navi 10 seems too small, 25% performance increase seems too small. I can see 2 reasons for it, 1 would be navi is still stuck at 64 Cus, but that seems to go against what other leaks have said, the other is that that sku is a cut down version of the core, what are your thoughts on it? 

 

The thing with AMD GPUs is that the design budgets appear to be derived from their Semi-Custom deals. AMD is probably best thought of a hybrid of a ODM with its own brand that it sells in certain markets. They sell more CPUs as Consoles and GPUs as OEM computers & Consoles than they do in the dGPU market. As a result, and as also seems obvious from all of the independent Polaris SKUs, they clearly can run up a number of GPU "designs" in record time. Nvidia is running about 5-6 separate GPU designs every 2-3 year cycle. AMD might be doing that many per year right now.

 

It's clear to me that AMD's Modular Design approach is really paying off. They can run out a "design" in probably 6 months compared to several years, if it's from a prepared design branch. The Consoles companies want new stuff, which is where the normal design cycle happens. As a result, the question is "when did Navi's Design Portfolio lock?". If it was back in late 2017, then AMD can roll out as many different designed-down versions of Navi as they want. Though I believe the Navi Chiplet for APUs was supposed to go to GloFo, which is what had to be officially moved to TSMC.  It's really easy to forget just how many of those APUs AMD actually sells, and continues to sell for a decade after launch. 

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