(transistors are nanotech)
We will be unable to make them smaller when every feature scales down to 1 atom thickness. but that is dependent on materials used. For silicon, the gate can get down to ~110pm which is 0.1nm. But we will obviously use different materials by then, so that can change
(of course this is just off the top of my head, im pretty sure you need to scale gates and drains similarly, as well as the interconnects between them, to maintain coherence, so there are more factors)