kynix

No, I am not a robot. Have you ever seen a robot read a book ? I think that is ridiculous.

yes, I love my circuit breaker. Sooooooo, do you love my circuit breaker ? thanks a lot.

But in whole they still belong to electronic parts.

How do you think english is not my first language ? thanks a lot.

I read an electronic magazine in which there is a report on what are the functional and structural characteristics of rack components . After reading, I became interested in rack components, so I searched some related materials and information about this topic, but found that it is not specific at all. Today I come to this forum to turn to you to discuss my understandings are appropriate. Here are my personal understandings: The rack component is a component used in the calender equipment to support and fix the calendar components. Such as roller, roller bearing, distance device and shaft cross device and other major parts, are fixed on the rack body or in the frame body sliding and rotation. The rack component is composed of main parts such as frame, base and connecting beam, and is fixed by screw connection. It has sufficient strength and rigidity to ensure that the parts on the rack body to work properly. Due to the number and arrangement of the calender roll, the structure of the frame is varied. Rack components in order to reduce the weight, most designed into a hollow structure, with ribs to ensure its support strength and rigidity. The surface roughness Ra of the composite contact plane of each part after machining is not more than 2.5μm The bearing housing window on the frame is used to mount the bearing housing of the roller. Note that the width of the bearing is larger than 50-60mm in diameter of the roller face to facilitate the passage of the roller and the bearing seat during the lifting of the installation. When the two sides of the window are machined, it is necessary to ensure that the two planes are parallel and perpendicular to the bottom plane. The surface roughness after processing should be no more than 2. Oμm. Rack components generally use HT350 gray pray iron cast forming rough, special requirements are also useful cast steel or ductile iron prayer forming blanks. Ps: Excuse me if I was wrong in words or expressions as I am a green hand in the field of rack components. I need continual learnings. What is your idea ? Do you agree with my ideas ? Any of your ideas would be highly appreciated. May someone would like to help ? thanks in advance.

I am so sorry that I don't get your points. Perhaps you need to seek some electronic forums to post it there. Hope that it is most useful to you. thanks for your question.

thanks for your comment. I will improve my passage based on your suggestion you made. thanks a lot.

Ok, I have got your meanings. I think that you can use the concept for more than 10 years or even longer. That is above the boundaries.

I am an electronic engineer in the field of circuit breakers and my job is working on various different electronic projects, such as circuit breakers. In recent days, I am making a project related to circuit breakers.Today I come to this forum to turn to you to discuss my understandings are appropriate. Here are my personal understandings: The line of fire in the circuit is connected to both ends of the switch. When the switch is placed in the ON state, the current flows from the bottom terminal, flows through the electromagnet, the movable contactor, the static contactor, and finally flows out from the top terminal. Current can magnetize electromagnets. The magnetic force generated by the electromagnet increases with the increase of the current, if the current decreases, the magnetic force will be weakened. When the current jumps to a dangerous level, the electromagnet produces a sufficiently large magnetic force to pull a metal rod connected to the switch interlock. This causes the mobile contactor to tilt and leave the static contactor, and then cut off the circuit. The current is interrupted. Bimetal design is based on the same principle, the difference is that there is no need to give the electromagnet energy, but the metal bar in the high current self-bending, and then start the linkage device. And some circuit breaker by filling the explosive material to move the switch. When the current exceeds a certain level, it will ignite the explosive material, and then drive the piston to open the switch. Rated current below 600A, and short-circuit current is not large, you can choose molded case circuit breaker; rated current, short circuit current is also large, should use universal circuit breaker. The general selection principle is: (1) circuit breaker rated current ≥ load working current; (2) the rated voltage of the circuit breaker ≥ the rated voltage of the power supply and load; (3) circuit breaker release rated current ≥ load working current; (4) circuit breaker limit breaking capacity ≥ circuit maximum short circuit current; (5) line single-phase short-circuit current / circuit breaker instantaneous (or short-circuit) release set current ≥ 1.25; (6) circuit breaker undervoltage release rated voltage = line rated voltage. Ps: Excuse me if I was wrong in words or expressions as I am a green hand in the field of circuit breakers. I need continual learnings. What is your idea ? Do you agree with my ideas ? Any of your ideas would be highly appreciated. May someone would like to help ? thanks in advance.

I am not a robot.

I read an electronic magazine in which there is a report on what are the working principles for time delay relays. After reading it, I became interested in time delay relays. So I searched some related materials and information, but found that it is not specific at all. Today I come to this forum to turn to you to discuss my understandings are appropriate. Here are my personal understandings: Time delay relay is a pulse delay principle to achieve the function of delay on-off relay, commonly used in relay protection and automation circuit, as the exchange of instantaneous action after the delay time to return to the time components. The working principles for time delay relays---circuit 1, The transistor relay delay circuit diagram: Figure 1 is a transistor composed of relay delay pull-in circuit. Just turn on the power, 16μF capacitor voltage is zero, the two transistors are cut off, the relay does not move. With the 16μF capacitor charging, after a period of time, the voltage reached a high level, the two transistors are turned on, the relay delay pull. Delay time up to 60s. The duration of the delay can be adjusted by a 10MΩ resistor. Figure 1 Transistor consisting of a relay delay pull-in circuit 2, The power delay relay circuit: This circuit utilizes the advantages of the base breakdown voltage of the transmitter / a common bipolar transistor. The reverse connection of the transmitter / base junction at the junction of a 2N3904 transistor as an 8 volt zener diode it creates a higher open connection to the Darlington transistor voltage. Almost all bipolar transistors can be used, but the zener voltage will likely be about 6 to 9 volts depending on the particular transistor used. The time is about 7 seconds to delay using a 47K resistor and a capacitor 100uF, which can be reduced by reducing the R or C value. The longer the delay can get a larger capacitance, the resistance time should not be increased in the past there may be 47K. The circuit should be connected to any 12 volt DC relay, with a 75 ohm resistor or multiple coils. The 10K resistor in the entire supply connection provides a power off when it is not needed if the power supply already has a discharge resistor, a capacitor discharge path. Figure 2 Power-up delay relay circuit 3. Time delay relay works - graphic symbols Figure 3 Graphical symbols for power-on delay relays Figure 4 Graphic symbols for power-off delay relays Ps: Excuse me if I was wrong in words or expressions as I am a green hand in the field of time delay relays. I need continual learnings. What is your idea ? Do you agree with my ideas ? Any of your ideas would be highly appreciated. May someone would like to help ? thanks in advance.

Why do you say that it is not a new concept ? thanks in advance.

I read an electronic magazine in which there is a report on the characteristics for field programmable gate arrays. After reading, I became interested in this topic, so I searched some materials and information about it, but found that it is not specific at all. Today I come to this forum to turn to you to discuss my understandings are appropriate. Here are my personal understandings: Field-programmable gate array (FPGA) is a programmable logic device, composed of thousands of exactly the same programmable logic unit, surrounded by the input / output unit composed of peripherals. It uses advanced computer-aided design technology for device development and design, its superiority far more than ordinary TTL integrated gate. Once the manufacturing is complete, the FPGA can be programmed at the job site to enable specific design functions. As to this question, what are the characteristics for field programmable gate arrays, I have my personal points of views: FPGA uses a new concept of logic cell array LCA (Logic Cell Array), including the configurable logic module CLB (Configurable Logic Block), output input module IOB (Input Output Block) and internal connection (Interconnect) three parts. The basic features of FPGA are: 1) FPGA design ASIC circuit, the user does not need to chip production, you can get a combination of chips. - 2) FPGA can do all other custom or semi-custom ASIC circuit of the sample sample. 3) FPGA has a rich internal trigger and I / O pin. 4) FPGA is the ASIC circuit design cycle of the shortest, the lowest cost of development, the risk of one of the smallest devices. 5) FPGA using high-speed CHMOS process, low power consumption, and CMOS, TTL level compatible. It can be said, FPGA chip is a small batch system to improve system integration, reliability, one of the best choice. Design, Implementation and Verification of Field Programmable Gate Array The design input is the logical relationship to be implemented in the way that the development system supports the input computer, which is the beginning of designing the FPGA. There are several ways to achieve design input, the most commonly used schematic editor. It allows design input in two ways: 1) Graphic input This input mode allows the use of various conventional gate circuits and logic components (macrocell) provided in the component library to design the circuit and input it in schematic mode; 2) Text input This input method allows the use of advanced programmable logic design language, such as VHDL, ABEL, CUPL language to write input files, but also allows the direct use of Boolean equations for input. The purpose of the design input is to generate an XNX (Xilinx Netlist Format) file, which is the design implementation and design validation of the input file. If both graphical input and text input are used, then merge (XNFMERGE) processing is required to produce a complete XNF file. Design implementation is the core of the design and development process, the main task is to merge the XNF file segmentation, layout and wiring. Segmentation is to XNF file in the logic design through the simplified, split into CLB and I / OB as the basic unit of the logic design. The layout is to assign the split logical design to the corresponding CLB and I / OB positions of the FPGA. Wiring is a good layout of the CLB, I / OB connection. Xilinx development software with automatic layout, cabling function, it can be in the layout, wiring process using a series of optimization procedures to find the best layout, wiring program. The ultimate goal of the design implementation is to produce a bitstream file that meets the design requirements. This is used to load binary files for FPGA chips. Design verification is mainly for the circuit simulation test. Simulation tests include functional simulation and real-time simulation. The functional simulation assumes that the signal produces the same delay time (0.1 ns) through each logic gate and that there is no delay through the path. This simulation can test whether the system function meets the design requirements. Real-time simulation is carried out after the layout and routing, it can be selected in accordance with the actual delay time of the device simulation, mainly used to verify the timing of the system. Design input, design implementation and design verification of the three parts alternately, and finally to fully meet the design requirements of the binary file. With this file by loading the cable or programming EPROM FPGA load, you can get the user needs ASIC chip. Developing trend for Field Programmable Gate Array With the development of microelectronics, EDA technology, and application system requirements, FPGAs are becoming a platform for digital system development and will continue to improve and improve in the following areas: (1) high integration, high capacity, low cost, low voltage, low power consumption; (2) resource diversification; (3) for on-chip systems: processors, high-speed serial I / O, DSP, etc.; (4) the use of deep submicron processes. Currently based on 90nm process FPGA has been commercial, is to advance to 65nm; (5) the development and improvement of various soft and hard IP library; (6) dynamic reconfigurable technology practical. Ps: Excuse me if I was wrong in words or expressions as I am a green hand in the field of FPGAs. I need continual learnings. What is your idea ? Do you agree with my ideas ? Any of your ideas would be highly appreciated. May someone would like to help ? thanks in advance.

I am an electronic engineer, always making different various projects and thinking about solutions to different questions. Today, I am going to make an electronic project related to RF shields for 3G mobile phones. Here are my following projects: The cellular transmitter module will generate the maximum radiated power for any component in the handset, which may induce EMI and RFI. Similar problems can be used to reduce RF and EMI associated with EMI and RFI The sensitivity to external magnetic fields can be minimized. So, what kind of shielding design method has the best efficiency? This three-part series discusses the effective RF shielding method around today's cellular transmitter modules. In recent years, mobile phones in the form, function, performance and cost have undergone tremendous changes. The evolving new technology has spawned smaller, more energy efficient and highly integrated semiconductor devices that continue to produce more portable (mobile) mobile products with more integrated levels. Operators are providing additional services such as SMS (SMS), multimedia (MMS) and GPS, while manufacturers add additional wireless features such as FM radio and other functions for mobile cellular phones, as well as MP3 players and digital cameras. Achieving all of these features requires a form factor and volume that poses a challenge to handset designers and hardware engineers. As a result, handset designers working on printed circuit board (PCB) levels are experiencing undesirable core issues such as coupling, coupling, and crosstalk between integrated devices. And all of these problems led to more design rework, the lack of versatility between the phone profile and the extended design cycle, and these have increased the cost of mobile phone development. In today's competitive market pressures, these factors play a key role in the success of mobile handset manufacturers and designers who develop them. One area in the early stages of handset design that could help solve these core problems is the widespread use of the shield. Shields reduce electromagnetic interference (EMI) and radio frequency interference (RFI), greatly weakening the unwanted radiation, alleviating the disaster it caused. At present, shielding and RF frequencies go hand in hand, because all RF communication standards have some requirement to minimize unwanted radiation. The effectiveness of the shield is characterized by its ability to attenuate the radiation signal in a wide spectral range. For example, a metal "container" with a movable cover may constitute a shield, or the container itself may be directly welded to the PCB. The use of a cover structure is useful for regulation, so it is often used in TV tuners and other applications, but the effectiveness of the shield is highly dependent on the electrical connection between the cover and the container. It is based on the basic concept of RF shielding: time-varying electromagnetic field (EM) will be in the conductor around the field line induced current. Therefore, the induced current in the perfect conductor will produce an EM field opposite to the evoked field, thereby canceling the field lines within the conductor. Therefore, shielding too many holes, grooves and openings will reduce the shielding effectiveness, which is due to the induced current can only exist in the conductor of free electrons flow. The opening on the conductor (container) means that there is no free electron there, which causes the current to flow along other paths along the opening, so that the induction field can not completely counteract the evoked field. The skin depth is another important factor, which is determined by the ability of the EM wave to penetrate the conductive membrane. In particular, when the low frequency is of particular importance, a thicker film will be required for effective shielding of the RF signal. Based on my project, I outlined a circuit and after testing over and over again, it worked well in the end. Ps: Excuse me if I was wrong improperly in words or expressions. I am a green hand in electronic engineerings. I need continual learnings. Those are just my understandings. What is your idea ? Do you agree with my ideas ? Any of your ideas would be highly appreciated. May someone would like to help ? thanks in advance.

Firstly, this is an instructional guide and ps: I outlined a circuit, attached with the topic, I have been puzzled about the circuit and don't know how to improve it. I do need your help.