looncraz

When you go to buy a video card are you concerned about which one has been on the market longer?

I've never been, beyond some maturity concerns with bleeding edge stuff.
 
The only issue with being late is that the ideal sales window has closed and the next generation of products will soon eclipse your products.
 
If Vega can deliver good performance at a reasonable price it will sell just as well as it would have if it had been released two months ago, but nowhere near as well as if it had come out prior to the Pascal cards.
 
We can all just hope that AMD has some secret sauce in the mix and they actually planned to leapfrog Pascal from the outset.  If not, Volta may prove to be too much for AMD to effectively counter... which means AMD can't make cheap enough CPUs to compete with a positive product margin.

When you go to buy a video card are you concerned about which one has been on the market longer?

I've never been, beyond some maturity concerns with bleeding edge stuff.
 
The only issue with being late is that the ideal sales window has closed and the next generation of products will soon eclipse your products.
 
If Vega can deliver good performance at a reasonable price it will sell just as well as it would have if it had been released two months ago, but nowhere near as well as if it had come out prior to the Pascal cards.
 
We can all just hope that AMD has some secret sauce in the mix and they actually planned to leapfrog Pascal from the outset.  If not, Volta may prove to be too much for AMD to effectively counter... which means AMD can't make cheap enough CPUs to compete with a positive product margin.

Each cpu die has 8 cores, 4 MB L2 cache and 16 MB L3 cache.
 
The 32 cores / 64 threads  has 4 such dies so there's going to be 16 MB L2 cache in total and 64 MB L3 cache (512 megabits).
 

It's most certainly not - the idiots looked at the misread L3 cache data in a leaked benchmark that stated 64MBx8 and have been claiming that means it has 512MB of L3... instead of just the program being unable to accurately read the cache configuration on an experimental chip...
 
A 16-core CPU should have 32MB of L3 cache, though, which is still plenty nice.

It's most certainly not - the idiots looked at the misread L3 cache data in a leaked benchmark that stated 64MBx8 and have been claiming that means it has 512MB of L3... instead of just the program being unable to accurately read the cache configuration on an experimental chip...
 
A 16-core CPU should have 32MB of L3 cache, though, which is still plenty nice.

yeah though they call it SMT
 
 
EDIT: simultaneous multithreading

SMT(hyperthreading) is different to modules.
 
Hyperthreading is one cores that shows as 2 or more threades to reduce bottlenecks inside the core
 
Modules have 2 Integer units, so they can do 2 streams of code at once, but they had only a singe FP unit. That design was't bad, it was implemented bad with a low ipc on a old process.

With the Bulldozer family of CPU architectures, AMD used something called CMT, which is somewhat different. It actually provides more hardware resources per "thread" than SMT.
 
But with the Zen architecture, they're switching to SMT, like Intel.
 
Note that hyperthreading/SMT isn't always utilized that well either. It's just much less of a problem because each Intel core, without hyperthreading, had plenty of performance. AMD's problem was their performance per core, and CMT was not really the cause of that (or at least not the only cause).

Whatever plant he lives on, it's gonna have to be one big plant. Sorry, i saw the opportunity and took it.
 
Any who, it's a bit deceptive to use time as a measure of performance when talking about Intel CPU's. They don't exactly change that much over the years, and highly clocked Ivy CPU's can still get down when it comes to most consumer related tasks. Haswell launched over 3 years ago, and if Zen showed Haswell IPC at similar clock speeds, they would only be 5% behind Skylake at similar clocks. Factor in the DDR4 support, and it makes Zen look slightly more appealing over Haswell. 
 
Again, most of this is speculation (because IPC numbers alone mean very little in the grand scheme of things) so take what I say with a grain of salt. If Zen can only deliver Ivy IPC, but can do so with similar core configurations to Haswell-E, DDR4, and a cheaper price, it will still be a win for most consumers. The biggest wild cards, are its IMC quality, overclocking/voltage tolerance (and potentially TIM quality), and the segmentation of the platform chipsets. That recent slide we saw regarding the many various Zen chipsets has me worried, with more than a few of them still having PCIE Gen 2 lanes. Hopefully we get more clarification on those topics soon. 

The nature of the L3 in Zen makes me believe they have a global concurrency system using the new data fabric.  Jim Keller designed such a system back in the day using HyperTransport (for inter-CPU communications and synchronization), so it would seem fitting for that system to have evolved into use for Zen for inter-CCX communications.  The penalty for globals should be rather low, maybe on the order of 5 cycles with two CCX, and another few cycles for each added CCX.  Hard to say at this point.
 
The L3 is "mostly" a victim cache, I'm suspecting it is used to store globally accessed data with tags.  If another CCX has the same data, there are many ways to guarantee that it remains synchronized (a hardware multiple reader single-writer (MRSW) implementation would have nearly zero cost for shared data on reads, but would add a potentially significant penalty on writes... but you're only talking about a few CCX-level locks maintained in the L3, which simplifies matters immensely).

AMD's own block diagram shows that the l3 cache is a (mostly) victim cache. A technical briefing by AMD even states that l3 is a victim cache: 
 

Less headroom relative to stock speed. That's what I meant. SKUs had higher stock speed overtime. But the OC ceiling stayed at the same 4,7Ghz to 5Ghz depending on the cooling solution, rather than  getting higher like the stock speeds. People expected the OC ceiling to increase with the stock speeds over time, which it didn't.

How do we know they gimped it "as much as they could"? I thought they only underclocked it to match the Zen SKU (for an attempt at an IPC comparison). Not only that, but I would take an open source bench to a closed source bench any day of the week. With how vague that demonstration was, we can't tell if it was in fact a custom workload. Even if it was, we don't know the details behind that either, so you can't say "we knew they skewed the test". We simply don't know. 

Personnally I don't think that thing is Zen,and since the gpu leaks of this summer I don't really buy into anything until it has been tested thoroughly by 3rd party reviewers. Even official info are bullshit when you think about it. Like polaris being the power efficiency reference and the 1060 3GB being a 1060.
Your theory would be funny but amd has said too much not to deliver on it. They'd be better off delaying rather than releasing a refresh
 

Do you know how far behind FX8350 IPC is? And have you seen Zen demo? To me, above post kind off adds up.
Final clocks are still unknown, don't know much they'll add to performance. But hopefully like FX chips like 4Ghz-4.3Ghz for highest clocked chip to compete.

Yeah, latest leaker (Admin of Chiphell) only reached max stable 480 reference overclock of 1340Mhz/8200Mhz. 
http://wccftech.com/radeon-rx-480-thermal-tests-leak/

 
either the silicon lottery is strong with Polaris, or the chiphell admin couldn't overclock to save their life.

If he is overclocking the reference card then that may be true,  remember it has only a 6 pin and 150w TDP. It well hit power limit  wall very easy.  Im more considered with the 300$ AIB ones,  how well those fair? . 

for 300 dollars they better be hitting 1600Mhz or it would be a waste.

Funny how the thought that this is a simple mistake made by Newegg, never crossed the minds of some people on here...

Or maybe each CU has  64 stream P's. And 64 CUDA cores. 

Why would their future not be Zen.

Long story short, it is difficult, or we'd stay with the same architecture with just mild tweaks each year.

One can't really blame Intel for AMDs inability to create competitive CPUs. Hopefully the Zen won't turn out to be just another paperweight.

You haven't watched the video have you, AMD started development on Bulldozer in the early 2000's, and it was a huge let down, AMD can't simply magic a new Architecture and have been forced to use Bulldozer. Not only was it slower it was also very expensive to make. Zen was designed by Jim Keller (need I explain this), it will be a smaller chip, meaning AMD can make more money off of it, you see now.

It was an informed guess, we know AMD is focusing on low power and efficiency with Polaris, and we know Nvidia will be focusing on compute, which will remove the efficiency advantage they have with Maxwell.